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Differential D128288

[PowerPC] Fix signatures for vec_replace_unaligned builtin
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Authored by lei on Jun 21 2022, 9:59 AM.

Details

Reviewers
amyk
quinnp
power-llvm-team
Commits
rGcaf7243a6b53: [PowerPC] Fix signatures for vec_replace_unaligned builtin
Summary

`vec_replace_unaligned` is meant to return vuc to emphasize that elements
are being inserted on unnatural boundaries.

Diff Detail

Event Timeline

lei created this revision.Jun 21 2022, 9:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 21 2022, 9:59 AM
Herald added subscribers: shchenz, nemanjai. · View Herald Transcript
lei requested review of this revision.Jun 21 2022, 9:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 21 2022, 9:59 AM
Harbormaster completed remote builds in B171128: Diff 438745.Jun 21 2022, 10:42 AM
quinnp accepted this revision.Jun 28 2022, 11:30 AM

LGTM. Thanks!

This revision is now accepted and ready to land.Jun 28 2022, 11:30 AM
amyk accepted this revision.Jun 28 2022, 11:35 AM

LGTM too. Thank you Lei.

Closed by commit rGcaf7243a6b53: [PowerPC] Fix signatures for vec_replace_unaligned builtin (authored by lei). · Explain WhyJun 29 2022, 7:36 AM
This revision was automatically updated to reflect the committed changes.
lei added a commit: rGcaf7243a6b53: [PowerPC] Fix signatures for vec_replace_unaligned builtin.

Revision Contents

PathSize
clang/
lib/
Headers/
24 lines
test/
CodeGen/
PowerPC/
48 lines
4 lines

Diff 441007

clang/lib/Headers/altivec.h

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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vec_blendv(vector double __a, vector double __b, vec_blendv(vector double __a, vector double __b,
vector unsigned long long __c) { vector unsigned long long __c) {
return (vector double)__builtin_vsx_xxblendvd( return (vector double)__builtin_vsx_xxblendvd(
(vector unsigned long long)__a, (vector unsigned long long)__b, __c); (vector unsigned long long)__a, (vector unsigned long long)__b, __c);
} }
#define vec_replace_unaligned(__a, __b, __c) \ #define vec_replace_unaligned(__a, __b, __c) \
_Generic((__a), vector signed int \ _Generic((__a), vector signed int \
: (vector signed int)__builtin_altivec_vinsw( \ : __builtin_altivec_vinsw((vector unsigned char)__a, \
(vector unsigned char)__a, (unsigned int)__b, __c), \ (unsigned int)__b, __c), \
vector unsigned int \ vector unsigned int \
: (vector unsigned int)__builtin_altivec_vinsw( \ : __builtin_altivec_vinsw((vector unsigned char)__a, \
(vector unsigned char)__a, (unsigned int)__b, __c), \ (unsigned int)__b, __c), \
vector unsigned long long \ vector unsigned long long \
: (vector unsigned long long)__builtin_altivec_vinsd( \ : __builtin_altivec_vinsd((vector unsigned char)__a, \
(vector unsigned char)__a, (unsigned long long)__b, __c), \ (unsigned long long)__b, __c), \
vector signed long long \ vector signed long long \
: (vector signed long long)__builtin_altivec_vinsd( \ : __builtin_altivec_vinsd((vector unsigned char)__a, \
(vector unsigned char)__a, (unsigned long long)__b, __c), \ (unsigned long long)__b, __c), \
vector float \ vector float \
: (vector float)__builtin_altivec_vinsw((vector unsigned char)__a, \ : __builtin_altivec_vinsw((vector unsigned char)__a, \
(unsigned int)__b, __c), \ (unsigned int)__b, __c), \
vector double \ vector double \
: (vector double)__builtin_altivec_vinsd( \ : __builtin_altivec_vinsd((vector unsigned char)__a, \
(vector unsigned char)__a, (unsigned long long)__b, __c)) (unsigned long long)__b, __c))
#define vec_replace_elt(__a, __b, __c) \ #define vec_replace_elt(__a, __b, __c) \
_Generic((__a), vector signed int \ _Generic((__a), vector signed int \
: (vector signed int)__builtin_altivec_vinsw_elt( \ : (vector signed int)__builtin_altivec_vinsw_elt( \
(vector unsigned char)__a, (unsigned int)__b, __c), \ (vector unsigned char)__a, (unsigned int)__b, __c), \
vector unsigned int \ vector unsigned int \
: (vector unsigned int)__builtin_altivec_vinsw_elt( \ : (vector unsigned int)__builtin_altivec_vinsw_elt( \
(vector unsigned char)__a, (unsigned int)__b, __c), \ (vector unsigned char)__a, (unsigned int)__b, __c), \
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c

Show First 20 Lines • Show All 1,177 Lines • ▼ Show 20 Lines
// CHECK-BE-LABEL: @test_vec_replace_unaligned_si( // CHECK-BE-LABEL: @test_vec_replace_unaligned_si(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_si( // CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vsia, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @sia, align 4
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]]
// //
vector signed int test_vec_replace_unaligned_si(void) { vector unsigned char test_vec_replace_unaligned_si(void) {
return vec_replace_unaligned(vsia, sia, 6); return vec_replace_unaligned(vsia, sia, 6);
} }
// CHECK-BE-LABEL: @test_vec_replace_unaligned_ui( // CHECK-BE-LABEL: @test_vec_replace_unaligned_ui(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <4 x i32> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_ui( // CHECK-LE-LABEL: @test_vec_replace_unaligned_ui(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* @vuia, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i32, i32* @uia, align 4
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[TMP2]], i32 8)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <4 x i32> [[TMP6]]
// //
vector unsigned int test_vec_replace_unaligned_ui(void) { vector unsigned char test_vec_replace_unaligned_ui(void) {
return vec_replace_unaligned(vuia, uia, 8); return vec_replace_unaligned(vuia, uia, 8);
} }
// CHECK-BE-LABEL: @test_vec_replace_unaligned_f( // CHECK-BE-LABEL: @test_vec_replace_unaligned_f(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 // CHECK-BE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4
// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <4 x float> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_f( // CHECK-LE-LABEL: @test_vec_replace_unaligned_f(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @vfa, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4 // CHECK-LE-NEXT: [[TMP2:%.*]] = load float, float* @fa, align 4
// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui float [[TMP2]] to i32
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> [[TMP3]], i32 [[CONV]], i32 12)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x float> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <4 x float> [[TMP6]]
// //
vector float test_vec_replace_unaligned_f(void) { vector unsigned char test_vec_replace_unaligned_f(void) {
return vec_replace_unaligned(vfa, fa, 12); return vec_replace_unaligned(vfa, fa, 12);
} }
// CHECK-BE-LABEL: @test_vec_replace_unaligned_sll( // CHECK-BE-LABEL: @test_vec_replace_unaligned_sll(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_sll( // CHECK-LE-LABEL: @test_vec_replace_unaligned_sll(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vslla, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @llb, align 8
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 6)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]]
// //
vector signed long long test_vec_replace_unaligned_sll(void) { vector unsigned char test_vec_replace_unaligned_sll(void) {
return vec_replace_unaligned(vslla, llb, 6); return vec_replace_unaligned(vslla, llb, 6);
} }
// CHECK-BE-LABEL: @test_vec_replace_unaligned_ull( // CHECK-BE-LABEL: @test_vec_replace_unaligned_ull(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 // CHECK-BE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <2 x i64> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_ull( // CHECK-LE-LABEL: @test_vec_replace_unaligned_ull(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vulla, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8 // CHECK-LE-NEXT: [[TMP2:%.*]] = load i64, i64* @ulla, align 8
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[TMP2]], i32 7)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x i64> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <2 x i64> [[TMP6]]
// //
vector unsigned long long test_vec_replace_unaligned_ull(void) { vector unsigned char test_vec_replace_unaligned_ull(void) {
return vec_replace_unaligned(vulla, ulla, 7); return vec_replace_unaligned(vulla, ulla, 7);
} }
// CHECK-BE-LABEL: @test_vec_replace_unaligned_d( // CHECK-BE-LABEL: @test_vec_replace_unaligned_d(
// CHECK-BE-NEXT: entry: // CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 // CHECK-BE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> // CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 // CHECK-BE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8
// CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-BE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64
// CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-BE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) // CHECK-BE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8)
// CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-BE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-BE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> // CHECK-BE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-BE-NEXT: ret <2 x double> [[TMP6]]
// //
// CHECK-LE-LABEL: @test_vec_replace_unaligned_d( // CHECK-LE-LABEL: @test_vec_replace_unaligned_d(
// CHECK-LE-NEXT: entry: // CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16 // CHECK-LE-NEXT: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @vda, align 16
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8> // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[TMP0]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8 // CHECK-LE-NEXT: [[TMP2:%.*]] = load double, double* @da, align 8
// CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64 // CHECK-LE-NEXT: [[CONV:%.*]] = fptoui double [[TMP2]] to i64
// CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
// CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8) // CHECK-LE-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> [[TMP3]], i64 [[CONV]], i32 8)
// CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8> // CHECK-LE-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <16 x i8>
// CHECK-LE-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <2 x double> // CHECK-LE-NEXT: ret <16 x i8> [[TMP5]]
// CHECK-LE-NEXT: ret <2 x double> [[TMP6]]
// //
vector double test_vec_replace_unaligned_d(void) { vector unsigned char test_vec_replace_unaligned_d(void) {
return vec_replace_unaligned(vda, da, 8); return vec_replace_unaligned(vda, da, 8);
} }
vector unsigned char test_vec_insertl_uc(void) { vector unsigned char test_vec_insertl_uc(void) {
// CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <16 x i8> // CHECK-BE-NEXT: ret <16 x i8>
// CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32 // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <16 x i8> // CHECK-LE-NEXT: ret <16 x i8>
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clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c

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} }
#elif defined(__TEST_ELT_D) #elif defined(__TEST_ELT_D)
vector double test_vec_replace_elt_d(void) { vector double test_vec_replace_elt_d(void) {
return vec_replace_elt(vda, da, 3); // expected-error {{element number 3 is outside of the valid range [0, 1]}} return vec_replace_elt(vda, da, 3); // expected-error {{element number 3 is outside of the valid range [0, 1]}}
} }
#elif defined(__TEST_UNALIGNED_UI) #elif defined(__TEST_UNALIGNED_UI)
vector unsigned int test_vec_replace_unaligned_ui(void) { vector unsigned char test_vec_replace_unaligned_ui(void) {
return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}} return vec_replace_unaligned(vuia, uia, 16); // expected-error {{byte number 16 is outside of the valid range [0, 12]}}
} }
#else #else
vector unsigned long long test_vec_replace_unaligned_ull(void) { vector unsigned char test_vec_replace_unaligned_ull(void) {
return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}} return vec_replace_unaligned(vulla, ulla, 12); // expected-error {{byte number 12 is outside of the valid range [0, 8]}}
} }
#endif #endif