llvm-reduce: Fix mangling types of generic registers

[arsenm]

e617d1a1d7f61bc639dd109e9844ebd3495333de

llvm/test/tools/llvm-reduce/mir/generic-vreg.mir

 # REQUIRES: amdgpu-registered-target
 # RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # Verify that reduction works with generic virtual registers, and the
 # properties like register banks, types and names.
 
 
 # CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
 # CHECK-INTERESTINGNESS: G_BITCAST
 # CHECK-INTERESTINGNESS: G_ADD
 # CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
 # CHECK-INTERESTINGNESS: G_STORE
 
-# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(p1), implicit-def %10(s64), implicit-def %11(s64)
-# RESULT-NEXT: %arst:_(<2 x s32>) = G_IMPLICIT_DEF
-# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %arst(<2 x s32>)
+# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(<2 x s16>), implicit-def %10(s64), implicit-def %11(s64), implicit-def %12(<2 x s32>)
+# RESULT-NEXT: %unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF
+# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %12(<2 x s32>)
 # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
 # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
 # RESULT-NEXT: G_STORE %v0(s32), %ptr(p1) :: (store (s32), addrspace 1)
-# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %v0(s32), implicit %11(s64)
+# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %9(<2 x s16>), implicit %11(s64)
 
 ---
 name:            f
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
     %v0:vgpr(s32) = COPY $vgpr0

llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir

 # CHECK-INTERESTINGNESS: G_STORE
 # CHECK-INTERESTINGNESS: G_STORE
 
 
 # RESULT: %{{[0-9]+}}:_(<2 x s16>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s16>) from %ir.argptr0, align 32, addrspace 1)
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1, addrspace 3)
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1 + 8, addrspace 3)
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1 + 12, align 4, basealign 8, addrspace 3)
-# RESULT: %{{[0-9]+}}:_(p3) = G_IMPLICIT_DEF
 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %fixed-stack.0, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %stack.0, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(p3), %{{[0-9]+}}(p3) :: (store (p3), addrspace 5)
-# RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p3) :: (load (s32) from call-entry @foo, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (load (s32) from call-entry @foo, addrspace 4)
 # RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p1) :: (load (s32) from constant-pool, addrspace 1)
-# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p3) :: (load (p1) from got, addrspace 4)
-# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p3) :: (load (p1) from jump-table, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from got, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from jump-table, addrspace 4)
 # RESULT: G_STORE %{{[0-9]+}}(<3 x s32>), %{{[0-9]+}}(p5) :: (store (<3 x s32>) into stack, align 8, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(<3 x s32>), %{{[0-9]+}}(p5) :: (store (<3 x s32>) into stack + 12, align 4, basealign 8, addrspace 5)
 --- |
   declare i32 @foo(i32)
 
   define void @func(<2 x i16> addrspace(1)* %argptr0, <2 x i32> addrspace(3)* %argptr1)  {
     ret void
   }

llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp

 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 using namespace llvm;
 
 static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
                                     MachineBasicBlock::reverse_iterator &RI,
-                                    const RegClassOrRegBank &RC,
+                                    const RegClassOrRegBank &RC, LLT Ty,
                                     SetVector<MachineInstr *> &ExcludeMIs) {
   auto MRI = &MBB.getParent()->getRegInfo();
   for (MachineBasicBlock::reverse_instr_iterator E = MBB.instr_rend(); RI != E;
        ++RI) {
     auto &MI = *RI;
     // All Def operands explicit and implicit.
     for (auto &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isDef())
         continue;
       auto Reg = MO.getReg();
       if (Register::isPhysicalRegister(Reg))
         continue;
 
-      if (MRI->getRegClassOrRegBank(Reg) == RC &&
+      if (MRI->getRegClassOrRegBank(Reg) == RC && MRI->getType(Reg) == Ty &&
           !ExcludeMIs.count(MO.getParent()))
         return Reg;
     }
   }
   return 0;
 }
 
 static void extractInstrFromFunction(Oracle &O, MachineFunction &MF) {
for (auto &MO : MI->operands()) {
         continue;
       auto Reg = MO.getReg();
       if (Register::isPhysicalRegister(Reg))
         continue;
       auto UI = MRI->use_begin(Reg);
       auto UE = MRI->use_end();
 
       const auto &RegRC = MRI->getRegClassOrRegBank(Reg);
+      LLT RegTy = MRI->getType(Reg);
+
       Register NewReg = 0;
       // If this is not a physical register and there are some uses.
       if (UI != UE) {
         MachineBasicBlock::reverse_iterator RI(*MI);
         MachineBasicBlock *BB = MI->getParent();
         ++RI;
         while (NewReg == 0 && BB) {
-          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, ToDelete);
+          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
           // Prepare for idom(BB).
           if (auto *IDM = MDT.getNode(BB)->getIDom()) {
             BB = IDM->getBlock();
             RI = BB->rbegin();
           } else {
             BB = nullptr;
           }
         }