llvm-reduce: Copy register allocation hints to clone

[qcolombet]

Nice catch!

[arsenm]

3217ca0863681c5e73e1e0f19e9de350249c45b8

llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir

+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# Make sure that register hints are preserved in the cloned function.
+
+# RESULT: registers:
+# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 5, class: vgpr_32, preferred-register: '$vgpr0' }
+# RESULT-NEXT: - { id: 6, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 7, class: vgpr_32, preferred-register: '%6' }
+# RESULT-NEXT: - { id: 8, class: vgpr_32, preferred-register: '%9' }
+# RESULT-NEXT: - { id: 9, class: vgpr_32, preferred-register: '%8' }
+---
+name: register_hints
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '%1' }
+  - { id: 3, class: vgpr_32, preferred-register: '%4' }
+  - { id: 4, class: vgpr_32, preferred-register: '%3' }
+body:             |
+  bb.0:
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    S_NOP 0
+    S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4
+
+...

llvm/tools/llvm-reduce/ReducerWorkItem.cpp

for (auto &SrcMI : SrcMBB) {
         LLT RegTy = SrcMRI->getType(SrcReg);
         if (RegTy.isValid())
           DstMRI->setType(DstReg, RegTy);
         Src2DstReg[SrcReg] = DstReg;
       }
     }
   }
 
+  // Copy register allocation hints.
+  for (std::pair<Register, Register> RegMapEntry : Src2DstReg) {
+    const auto &Hints = SrcMRI->getRegAllocationHints(RegMapEntry.first);
+    for (Register PrefReg : Hints.second) {
+      if (PrefReg.isVirtual()) {
+        auto PrefRegEntry = Src2DstReg.find(PrefReg);
+        assert(PrefRegEntry !=Src2DstReg.end());
+        DstMRI->addRegAllocationHint(RegMapEntry.second, PrefRegEntry->second);
+      } else
+        DstMRI->addRegAllocationHint(RegMapEntry.second, PrefReg);
+    }
+  }
+
   // Clone blocks.
   for (auto &SrcMBB : *SrcMF)
     Src2DstMBB[&SrcMBB] = DstMF->CreateMachineBasicBlock();
   // Link blocks.
   for (auto &SrcMBB : *SrcMF) {
     auto *DstMBB = Src2DstMBB[&SrcMBB];
     DstMF->push_back(DstMBB);
     for (auto It = SrcMBB.succ_begin(), IterEnd = SrcMBB.succ_end();