[MIPS64] Emulate MSA branch instructions

[slthakur]

Summary

This patch adds MSA branch instruction emulation for MIPS64.

[jaydeep]

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

3117

This should be pc + 8. If branch is not taken then we need to skip the delay slot.

[tberghammer]

You added 10 new function to the emulator where the first 8 functions and the last 2 functions are almost identical. I know that the rest of the MIPS64 instruction emulator is having the same issue but I would like to see these functions to be merged into a smaller number of functions to remove code duplication.

I see 2 different approach to do it and I am not sure which one is better in this case, but both of them improves the situation by a lot.

• Write only 2 function (first 8, last 2) and that function then reads out the condition and the sizes from the MCInst object. I would prefer this approach, but I am not sure how difficult it is to read out data from an MCInst
• Keep the 10 function for the 10 different instruction, but make these functions to call a function (one for the first 8 and one for the last 2) with passing in the constants required by the specific instruction.

Both approach would reduce the amount of code in this class and help a lot in reducing the maintenance cost with removing a lot of duplicated code.

[clayborg]

I will defer to MIPS experts here. You might thing about adding tberghammer as a reviewer.

[slthakur]

Addressed review comments

[tberghammer]

I don't know too much about mips so I haven't checked if the emulation is actually correct but the general concept looks good to me. I added a few comments inline but they are mostly suggestions what you might want to consider.

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

553–562

(nit): Indentation

3138–3140

Please initialize these variables

3160

You can possibly write it in the following way, but I am not sure which one is the cleaner:

if((*ptr == 0) == bnz)
    break;

3187

Using eContextInvalid as context type is fine for single stepping but if you want these instructions to be handled correctly during emulation based stack unwinding then you have to use eContextAbsoluteBranchRegister or eContextRelativeBranchImmediate with the correct data (it is used by the branch following code in the unwinder)

3211–3213

Please initialize these variables

3230

You can possibly write it in the following way, but I am not sure which one is the cleaner:

if(llvm::APInt::isSameValue(zero_value, wr_val) != bnz)
    ...

3236

Using eContextInvalid as context type is fine for single stepping but if you want these instructions to be handled correctly during emulation based stack unwinding then you have to use eContextAbsoluteBranchRegister or eContextRelativeBranchImmediate with the correct data (it is used by the branch following code in the unwinder)

[slthakur]

Addressed review comments

[slthakur]

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

3160

The former one is more readable.

3187

I have set the type to eContextRelativeBranchImmediate for now we are using these instructions for single stepping only.

3230

The former one is more readable.

3236

I have set the type to eContextRelativeBranchImmediate for now we are using these instructions for single stepping only.

[slthakur]

Corrected code indent and initialized wr_val correctly.

[tberghammer]

LGTM

[jaydeep]

Looks good to me

[slthakur]

Committed in revision 246745

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

     Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
     bool
+    Emulate_BNZB  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZH  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZW  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZD  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZB  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZH  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZW  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZD  (llvm::MCInst& insn);
+
+    bool
+    Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+    bool
+    Emulate_BNZV  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZV  (llvm::MCInst& insn);
+
+    bool
+    Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+    bool
     nonvolatile_reg_p (uint64_t regnum);
 
     const char *

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

             case gcc_dwarf_f29_mips64: return "f29";
             case gcc_dwarf_f30_mips64: return "f30";
             case gcc_dwarf_f31_mips64: return "f31";
+            case gcc_dwarf_w0_mips64:  return "w0";
+            case gcc_dwarf_w1_mips64:  return "w1";
+            case gcc_dwarf_w2_mips64:  return "w2";
+            case gcc_dwarf_w3_mips64:  return "w3";
+            case gcc_dwarf_w4_mips64:  return "w4";
+            case gcc_dwarf_w5_mips64:  return "w5";
+            case gcc_dwarf_w6_mips64:  return "w6";
+            case gcc_dwarf_w7_mips64:  return "w7";
+            case gcc_dwarf_w8_mips64:  return "w8";
+            case gcc_dwarf_w9_mips64:  return "w9";
+            case gcc_dwarf_w10_mips64: return "w10";
+            case gcc_dwarf_w11_mips64: return "w11";
+            case gcc_dwarf_w12_mips64: return "w12";
+            case gcc_dwarf_w13_mips64: return "w13";
+            case gcc_dwarf_w14_mips64: return "w14";
+            case gcc_dwarf_w15_mips64: return "w15";
+            case gcc_dwarf_w16_mips64: return "w16";
+            case gcc_dwarf_w17_mips64: return "w17";
+            case gcc_dwarf_w18_mips64: return "w18";
+            case gcc_dwarf_w19_mips64: return "w19";
+            case gcc_dwarf_w20_mips64: return "w20";
+            case gcc_dwarf_w21_mips64: return "w21";
+            case gcc_dwarf_w22_mips64: return "w22";
+            case gcc_dwarf_w23_mips64: return "w23";
+            case gcc_dwarf_w24_mips64: return "w24";
+            case gcc_dwarf_w25_mips64: return "w25";
+            case gcc_dwarf_w26_mips64: return "w26";
+            case gcc_dwarf_w27_mips64: return "w27";
+            case gcc_dwarf_w28_mips64: return "w28";
+            case gcc_dwarf_w29_mips64: return "w29";
+            case gcc_dwarf_w30_mips64: return "w30";
+            case gcc_dwarf_w31_mips64: return "w31";
+            case gcc_dwarf_mir_mips64: return "mir";
+            case gcc_dwarf_mcsr_mips64: return "mcsr";
+            case gcc_dwarf_config5_mips64: return "config5";
             default:
                 break;
         }

         case gcc_dwarf_f31_mips64:      return "f31";
         case gcc_dwarf_fcsr_mips64:     return "fcsr";
         case gcc_dwarf_fir_mips64:      return "fir";
+        case gcc_dwarf_w0_mips64:       return "w0";
+        case gcc_dwarf_w1_mips64:       return "w1";
+        case gcc_dwarf_w2_mips64:       return "w2";
+        case gcc_dwarf_w3_mips64:       return "w3";
+        case gcc_dwarf_w4_mips64:       return "w4";
+        case gcc_dwarf_w5_mips64:       return "w5";
+        case gcc_dwarf_w6_mips64:       return "w6";
+        case gcc_dwarf_w7_mips64:       return "w7";
+        case gcc_dwarf_w8_mips64:       return "w8";
+        case gcc_dwarf_w9_mips64:       return "w9";
+        case gcc_dwarf_w10_mips64:      return "w10";
+        case gcc_dwarf_w11_mips64:      return "w11";
+        case gcc_dwarf_w12_mips64:      return "w12";
+        case gcc_dwarf_w13_mips64:      return "w13";
+        case gcc_dwarf_w14_mips64:      return "w14";
+        case gcc_dwarf_w15_mips64:      return "w15";
+        case gcc_dwarf_w16_mips64:      return "w16";
+        case gcc_dwarf_w17_mips64:      return "w17";
+        case gcc_dwarf_w18_mips64:      return "w18";
+        case gcc_dwarf_w19_mips64:      return "w19";
+        case gcc_dwarf_w20_mips64:      return "w20";
+        case gcc_dwarf_w21_mips64:      return "w21";
+        case gcc_dwarf_w22_mips64:      return "w22";
+        case gcc_dwarf_w23_mips64:      return "w23";
+        case gcc_dwarf_w24_mips64:      return "w24";
+        case gcc_dwarf_w25_mips64:      return "w25";
+        case gcc_dwarf_w26_mips64:      return "w26";
+        case gcc_dwarf_w27_mips64:      return "w27";
+        case gcc_dwarf_w28_mips64:      return "w28";
+        case gcc_dwarf_w29_mips64:      return "w29";
+        case gcc_dwarf_w30_mips64:      return "w30";
+        case gcc_dwarf_w31_mips64:      return "w31";
+        case gcc_dwarf_mcsr_mips64:     return "mcsr";
+        case gcc_dwarf_mir_mips64:      return "mir";
+        case gcc_dwarf_config5_mips64:  return "config5";
     }
     return nullptr;
 }

        ::memset (&reg_info, 0, sizeof(RegisterInfo));
        ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
-       if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64)
+       if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64 || reg_num == gcc_dwarf_mcsr_mips64 || reg_num == gcc_dwarf_mir_mips64 || reg_num == gcc_dwarf_config5_mips64)
        {
            reg_info.byte_size = 4;
            reg_info.format = eFormatHex;

            reg_info.format = eFormatHex;
            reg_info.encoding = eEncodingUint;
        }
+       else if ((int)reg_num >= gcc_dwarf_w0_mips64 && (int)reg_num <= gcc_dwarf_w31_mips64)
+       {
+           reg_info.byte_size = 16;
+           reg_info.format = eFormatVectorOfUInt8;
+           reg_info.encoding = eEncodingVector;
+       }
        else
        {
            return false;

         { "BC1ANY2T",   &EmulateInstructionMIPS64::Emulate_BC1ANY2T,    "BC1ANY2T cc, offset"       },
         { "BC1ANY4F",   &EmulateInstructionMIPS64::Emulate_BC1ANY4F,    "BC1ANY4F cc, offset"       },
         { "BC1ANY4T",   &EmulateInstructionMIPS64::Emulate_BC1ANY4T,    "BC1ANY4T cc, offset"       },
+        { "BNZ_B",     &EmulateInstructionMIPS64::Emulate_BNZB,        "BNZ.b wt,s16"             },
+        { "BNZ_H",     &EmulateInstructionMIPS64::Emulate_BNZH,        "BNZ.h wt,s16"             },
+        { "BNZ_W",     &EmulateInstructionMIPS64::Emulate_BNZW,        "BNZ.w wt,s16"             },
+        { "BNZ_D",     &EmulateInstructionMIPS64::Emulate_BNZD,        "BNZ.d wt,s16"             },
+        { "BZ_B",      &EmulateInstructionMIPS64::Emulate_BZB,         "BZ.b wt,s16"              },
+        { "BZ_H",      &EmulateInstructionMIPS64::Emulate_BZH,         "BZ.h wt,s16"              },
+        { "BZ_W",      &EmulateInstructionMIPS64::Emulate_BZW,         "BZ.w wt,s16"              },
+        { "BZ_D",      &EmulateInstructionMIPS64::Emulate_BZD,         "BZ.d wt,s16"              },
+        { "BNZ_V",     &EmulateInstructionMIPS64::Emulate_BNZV,        "BNZ.V wt,s16"              },
+        { "BZ_V",      &EmulateInstructionMIPS64::Emulate_BZV,         "BZ.V wt,s16"               },
     };
 
     static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);

 
     return true;
 }
+
+bool
+EmulateInstructionMIPS64::Emulate_BNZB (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 1, true);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BNZH (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 2, true);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BNZW (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 4, true);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BNZD (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 8, true);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BZB (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 1, false);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BZH (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 2, false);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BZW (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 4, false);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BZD (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 8, false);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz)
+{
+    bool success = false, branch_hit = true;
+    uint32_t wt;
+    int64_t offset, pc, target;
+    RegisterValue reg_value;
+    uint8_t * ptr = NULL;
+
+    wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips64 + wt, reg_value))
+        ptr = (uint8_t *)reg_value.GetBytes();
+    else
+        return false;
+
+    for(int i = 0; i < 16 / element_byte_size; i++)
+    {
+        switch(element_byte_size)
+        {
+            case 1:
+                if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
+                    branch_hit = false;
+                break;
+            case 2:
+                if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+            case 4:
+                if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+            case 8:
+                if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+        }
+        if(!branch_hit)
+           break;
+        ptr = ptr + element_byte_size;
+    }
+
+    if(branch_hit)
+        target = pc + offset;
+    else
+        target = pc + 8;
+
+    Context context;
+    context.type = eContextInvalid;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BNZV (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_V (insn, true);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BZV (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_V (insn, false);
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz)
+{
+    bool success = false;
+    uint32_t wt;
+    int64_t offset, pc, target;
+    llvm::APInt wr_val;
+    llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
+    llvm::APInt zero_value = llvm::APInt::getNullValue(128);
+    RegisterValue reg_value;
+
+    wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips64 + wt, reg_value))
+        wr_val = reg_value.GetAsUInt128(fail_value);
+    else
+        return false;
+
+    if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
+        target = pc + offset;
+    else
+        target = pc + 8;
+
+    Context context;
+    context.type = eContextInvalid;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}