[z/OS] Clean up some z/OS testcases.

[Everybody0523]

Summary

This patch does some cleanup on several z/OS testcases. In particular, CHECK is replaced with CHECK-DAG in many places where the exact ordering of the instructions checked for does not matter. This allows for avoiding test failures in semi-related changes.

[uweigand]

llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

17

This may be a bit too flexible. The CHECK-DAG here would allow the two instructions above to be swapped, in which case the semantics would be incorrect.

The same holds for a number of other tests below. Maybe a better way would be to use auto-generated CHECK statements for this file? (Via utils/update_llc_test_checks.py)

llvm/test/CodeGen/SystemZ/call-zos-01.ll

entry:
   %ret = call fp128 (fp128) @pass_longdouble(fp128 0xLE0FC1518450562CD4000921FB5444261)
   ret fp128 %ret
 }
 
 ; CHECK-LABEL: call_floats0
 ; CHECK: larl  [[GENREG:[0-9]+]], @{{CPI[0-9]+_[0-9]+}}
 ; CHECK-NEXT: ld  1, 0([[GENREG]])
 ; CHECK-NEXT: ld  3, 8([[GENREG]])
-; CHECK: lxr 5, 0
+; CHECK: lxr [[TEMPFPR:[0-9]+]], 0
 ; CHECK: lxr 0, 1
-; CHECK: lxr 4, 5
+; CHECK: lxr 4, [[TEMPFPR]]
 define i64 @call_floats0(fp128 %arg0, double %arg1) {
 entry:
   %ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1)
   ret i64 %ret
 }
 
 ; CHECK-LABEL: call_floats1
 ; CHECK: lxr 1, 0

llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

 ; Test passing variable argument lists in 64-bit calls on z/OS.
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
 ; CHECK-LABEL: call_vararg_double0
 ; CHECK:       llihf 3, 1074118262
 ; CHECK-NEXT:  oilf  3, 3367254360
 ; CHECK:       lghi  1, 1
 ; CHECK:       lghi  2, 2
 define i64 @call_vararg_double0() {
 entry:
   %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, double 2.718000e+00)
   ret i64 %retval
 }
 
 ; CHECK-LABEL:  call_vararg_double1
-; CHECK:        llihf 0, 1074118262
-; CHECK-NEXT:   oilf  0, 3367254360
-; CHECK:        llihf 3, 1074340036
-; CHECK-NEXT:   oilf  3, 2611340116
-; CHECK:        lghi  1, 1
-; CHECK:        lghi  2, 2
-; CHECK:        stg 0, 2200(4)
+; CHECK-DAG:   llihf 0, 1074118262
+; CHECK-DAG:   oilf  0, 3367254360
+; CHECK-DAG:   llihf 3, 1074340036
+; CHECK-DAG:   oilf  3, 2611340116
+; CHECK-DAG:   lghi  1, 1
+; CHECK-DAG:   lghi  2, 2
+; CHECK-DAG:   stg 0, 2200(4)
 define i64 @call_vararg_double1() {
 entry:
   %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, double 3.141000e+00, double 2.718000e+00)
   ret i64 %retval
 }
 
 ; CHECK-LABEL: call_vararg_double2
 ; CHECK-NOT:   llihf 0
 ; CHECK-NOT:   oilf 0
 ; CHECK:       llihf 2, 1074118262
 ; CHECK-NEXT:  oilf  2, 3367254360
 ; CHECK:       lghi  1, 8200
 define i64 @call_vararg_double2() {
 entry:
   %retval = call i64 (i64, ...) @pass_vararg2(i64 8200, double 2.718000e+00)
   ret i64 %retval
 }
 
 ; CHECK-LABEL: call_vararg_double3
-; CHECK:       llihf   0, 1072703839
-; CHECK-NEXT:  oilf    0, 2861204133
-; CHECK:       llihf   1, 1074118262
-; CHECK-NEXT:  oilf    1, 3367254360
-; CHECK:       llihf   2, 1074340036
-; CHECK-NEXT:  oilf    2, 2611340116
-; CHECK:       llihf   3, 1073127358
-; CHECK-NEXT:  oilf    3, 1992864825
-; CHECK:       stg     0, 2200(4)
+; CHECK-DAG:  llihf   0, 1072703839
+; CHECK-DAG:  oilf    0, 2861204133
+; CHECK-DAG:  llihf   1, 1074118262
+; CHECK-DAG:  oilf    1, 3367254360
+; CHECK-DAG:  llihf   2, 1074340036
+; CHECK-DAG:  oilf    2, 2611340116
+; CHECK-DAG:  llihf   3, 1073127358
+; CHECK-DAG:  oilf    3, 1992864825
+; CHECK-DAG:  stg     0, 2200(4)
 define i64 @call_vararg_double3() {
 entry:
   %retval = call i64 (...) @pass_vararg3(double 2.718000e+00, double 3.141000e+00, double 1.414000e+00, double 1.010101e+00)
   ret i64 %retval
 }
 
 ; CHECK-LABEL: call_vararg_both0
 ; CHECK:       lgr   2, 1
 ; CHECK:       lgdr  1, 0
 define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
   %retval  = call i64(...) @pass_vararg3(double %arg1, i64 %arg0)
   ret i64 %retval
 }
 
 ; CHECK-LABEL: call_vararg_long_double0
 ; CHECK:       larl  1, @CPI5_0
 ; CHECK-NEXT:  ld    0, 0(1)
 ; CHECK-NEXT:  ld    2, 8(1)
-; CHECK-NEXT:  lgdr  3, 0
-; CHECK:       lghi  1, 1
-; CHECK:       lghi  2, 2
-; CHECK:       std   0, 2192(4)
-; CHECK-NEXT:  std   2, 2200(4)
+; CHECK-DAG:       lgdr  3, 0
+; CHECK-DAG:       lghi  1, 1
+; CHECK-DAG:       lghi  2, 2
+; CHECK-DAG:       std   0, 2192(4)
+; CHECK-DAG:       std   2, 2200(4)
 define i64 @call_vararg_long_double0() {
 entry:
   %retval = call i64 (i64, i64, ...) @pass_vararg0(i64 1, i64 2, fp128 0xLE0FC1518450562CD4000921FB5444261)
   ret i64 %retval
 }
 
 ; CHECK-LABEL: call_vararg_long_double1
 ; CHECK:       lgdr  3, 0

 define void @call_vec_vararg_test0(<2 x double> %v) {
   %retval = call i64(i64, ...) @pass_vararg2(i64 1, <2 x double> %v)
   ret void
 }
 
 ; ARCH12-LABEL: call_vec_vararg_test1
 ; ARCH12: larl  1, @CPI10_0
 ; ARCH12: vl    0, 0(1), 3
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: vrepg 2, 0, 1
-; ARCH12: vst   25, 2208(4), 3
-; ARCH12: vst   24, 2192(4), 3
+; ARCH12-DAG: vlgvg 3, 24, 0
+; ARCH12-DAG: vrepg 2, 0, 1
+; ARCH12-DAG: vst   25, 2208(4), 3
+; ARCH12-DAG: vst   24, 2192(4), 3
 define void @call_vec_vararg_test1(<4 x i32> %v, <2 x i64> %w) {
   %retval = call i64(fp128, ...) @pass_vararg1(fp128 0xLE0FC1518450562CD4000921FB5444261, <4 x i32> %v, <2 x i64> %w)
   ret void
 }
 
 ; ARCH12-LABEL: call_vec_char_vararg_straddle
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: lghi  1, 1
-; ARCH12: lghi  2, 2
-; ARCH12: vst   24, 2192(4), 3
+; ARCH12-DAG: vlgvg 3, 24, 0
+; ARCH12-DAG: vst   24, 2192(4), 3
+; ARCH12-DAG: lghi  1, 1
+; ARCH12-DAG: lghi  2, 2
 define void @call_vec_char_vararg_straddle(<16 x i8> %v) {
   %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <16 x i8> %v)
   ret void
 }
 
 ; ARCH12-LABEL: call_vec_short_vararg_straddle
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: lghi  1, 1
-; ARCH12: lghi  2, 2
-; ARCH12: vst   24, 2192(4), 3
+; ARCH12-DAG: vlgvg 3, 24, 0
+; ARCH12-DAG: vst   24, 2192(4), 3
+; ARCH12-DAG: lghi  1, 1
+; ARCH12-DAG: lghi  2, 2
 define void @call_vec_short_vararg_straddle(<8 x i16> %v) {
   %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <8 x i16> %v)
   ret void
 }
 
 ; ARCH12-LABEL: call_vec_int_vararg_straddle
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: lghi  1, 1
-; ARCH12: lghi  2, 2
-; ARCH12: vst 24, 2192(4), 3
+; ARCH12-DAG: vlgvg 3, 24, 0
+; ARCH12-DAG: vst 24, 2192(4), 3
+; ARCH12-DAG: lghi  1, 1
+; ARCH12-DAG: lghi  2, 2
 define void @call_vec_int_vararg_straddle(<4 x i32> %v) {
   %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <4 x i32> %v)
   ret void
 }
 
 ; ARCH12-LABEL: call_vec_double_vararg_straddle
-; ARCH12: vlgvg 3, 24, 0
-; ARCH12: lghi  1, 1
-; ARCH12: lghi  2, 2
-; ARCH12: vst 24, 2192(4), 3
+; ARCH12-DAG: vlgvg 3, 24, 0
+; ARCH12-DAG: vst 24, 2192(4), 3
+; ARCH12-DAG: lghi  1, 1
+; ARCH12-DAG: lghi  2, 2
 define void @call_vec_double_vararg_straddle(<2 x double> %v) {
   %retval = call i64(i64, i64, ...) @pass_vararg0(i64 1, i64 2, <2 x double> %v)
   ret void
 }
 
 ; CHECK-LABEL: call_vararg_integral0
 ; Since arguments 0, 1, and 2 are already in the correct
 ; registers, we should have no loads of any sort into

llvm/test/CodeGen/SystemZ/call-zos-vec.ll

 entry:
   %ret = call i64 (<2 x i64>, i64) @pass_vecs0(<2 x i64> %v1, i64 %n)
   ret i64 %ret
 }
 
 ; Verify that 3 is not allocated for passing integral types
 ; if 24 and %f0 are used.
 ; CHECK-LABEL: call_vecs1
-; CHECK: vlr 24, 25
-; CHECK: stg 1, 2200(4)
+; CHECK-DAG: vlr 24, 25
+; CHECK-DAG: stg 1, 2200(4)
 define i64 @call_vecs1(i64 %n, <2 x i64> %v1, double %x, <2 x i64> %v2) {
 entry:
   %ret = call i64 (<2 x i64>, double, i64) @pass_vecs1(<2 x i64> %v2, double %x, i64 %n)
   ret i64 %ret
 }
 
 ; Verify that 3 is not allocated for passing integral types
 ; if 24 and 25 are used.

llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll

define i64 @func4(i64 %n) {
   %call = call i64 @fun2(i64 %n, i64* nonnull %vla, i64* nonnull %vla)
   ret i64 %call
 }
 
 ; Require saving of r4 and in addition, a displacement large enough
 ; to force use of agfi before stmg.
 ; CHECK64: lgr  0, 4
 ; CHECK64: agfi 4, -1040192
-; CHECK64: stmg  4, 9, 2048(4)
-; CHECK64: lgr     8, 4
+; CHECK64-DAG: stmg  4, 9, 2048(4)
+; CHECK64-DAG: lgr     8, 4
 ; TODO Will change to basr with ADA introduction.
 ; CHECK64: brasl   7, @@ALCAXP
 ; CHECK64-NEXT: bcr     0, 3
 ;; CHECK64: lmg 4, 9, 2048(4)
 define i64 @func5(i64 %n) {
   %vla = alloca i64, i64 %n, align 8
   %arr = alloca [130000 x i64], align 8
   %ptr = bitcast [130000 x i64]* %arr to i64*