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Differential D121799

[VE] Remove output to /dev/stdout
ClosedPublic

Authored by Jake-Egan on Mar 16 2022, 6:39 AM.

Details

Reviewers
simoll
kaz7
hubert.reinterpretcast
Commits
rGc7dc9dbaff3a: [VE] Remove output to /dev/stdout
Summary

Sending output to /dev/stdout on AIX gets an llc permission denied error, so this patch removes this from the tests.

Diff Detail

Event Timeline

Jake-Egan created this revision.Mar 16 2022, 6:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 16 2022, 6:39 AM
Jake-Egan requested review of this revision.Mar 16 2022, 6:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 16 2022, 6:39 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Jake-Egan edited the summary of this revision. (Show Details)Mar 16 2022, 6:42 AM
Jake-Egan added reviewers: simoll, kaz7.
simoll accepted this revision.Mar 16 2022, 6:59 AM

I always wondered why we are doing the <..

This revision is now accepted and ready to land.Mar 16 2022, 6:59 AM
hubert.reinterpretcast accepted this revision.Mar 16 2022, 7:20 AM
hubert.reinterpretcast added a subscriber: hubert.reinterpretcast.

LGTM by the way. The use of /dev/stdout would cause grief for Windows too?

Harbormaster completed remote builds in B154586: Diff 415807.Mar 16 2022, 7:57 AM
This revision was landed with ongoing or failed builds.Mar 16 2022, 8:42 AM
Closed by commit rGc7dc9dbaff3a: [VE] Remove output to /dev/stdout (authored by Jake-Egan). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jake-Egan added a commit: rGc7dc9dbaff3a: [VE] Remove output to /dev/stdout.

Revision Contents

Diff 415850

llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>) declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>)
define fastcc i64 @vec_reduce_add_v256i64(<256 x i64> %v) { define fastcc i64 @vec_reduce_add_v256i64(<256 x i64> %v) {
; CHECK-LABEL: vec_reduce_add_v256i64: ; CHECK-LABEL: vec_reduce_add_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 ; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
Show All 25 Lines

llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>) declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>)
define fastcc i64 @vec_reduce_and_v256i64(<256 x i64> %v) { define fastcc i64 @vec_reduce_and_v256i64(<256 x i64> %v) {
; CHECK-LABEL: vec_reduce_and_v256i64: ; CHECK-LABEL: vec_reduce_and_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 ; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
Show All 25 Lines

llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>) declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>)
define fastcc i64 @vec_reduce_or_v256i64(<256 x i64> %v) { define fastcc i64 @vec_reduce_or_v256i64(<256 x i64> %v) {
; CHECK-LABEL: vec_reduce_or_v256i64: ; CHECK-LABEL: vec_reduce_or_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 ; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
Show All 25 Lines

llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>) declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>)
define fastcc i64 @vec_reduce_smax_v256i64(<256 x i64> %v) { define fastcc i64 @vec_reduce_smax_v256i64(<256 x i64> %v) {
; CHECK-LABEL: vec_reduce_smax_v256i64: ; CHECK-LABEL: vec_reduce_smax_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 ; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
Show All 25 Lines

llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>) declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)
define fastcc i64 @vec_reduce_xor_v256i64(<256 x i64> %v) { define fastcc i64 @vec_reduce_xor_v256i64(<256 x i64> %v) {
; CHECK-LABEL: vec_reduce_xor_v256i64: ; CHECK-LABEL: vec_reduce_xor_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256 ; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 ; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
Show All 25 Lines

llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32) declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32)
define fastcc i64 @vp_reduce_add_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) { define fastcc i64 @vp_reduce_add_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_add_v256i64: ; CHECK-LABEL: vp_reduce_add_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1 ; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
Show All 31 Lines

llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32) declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
define fastcc i64 @vp_reduce_and_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) { define fastcc i64 @vp_reduce_and_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_and_v256i64: ; CHECK-LABEL: vp_reduce_and_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1 ; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
Show All 31 Lines

llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32) declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32)
define fastcc i64 @vp_reduce_or_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) { define fastcc i64 @vp_reduce_or_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_or_v256i64: ; CHECK-LABEL: vp_reduce_or_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1 ; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
Show All 31 Lines

llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32) declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32)
define fastcc i64 @vp_reduce_smax_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) { define fastcc i64 @vp_reduce_smax_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_smax_v256i64: ; CHECK-LABEL: vp_reduce_smax_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1 ; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
Show All 31 Lines

llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 --march=ve -mattr=+vpu %s -o=/dev/stdout | FileCheck %s ; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32) declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32)
define fastcc i64 @vp_reduce_xor_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) { define fastcc i64 @vp_reduce_xor_v256i64(i64 %s, <256 x i64> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_xor_v256i64: ; CHECK-LABEL: vp_reduce_xor_v256i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1 ; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
Show All 31 Lines