[VE] v512|256 f32|64 fneg isel and tests

[simoll]

Summary

fneg instruction isel and tests. We do this also in preparation of fused negatate-multiple-add fp operations.

[simoll]

Add missing tests

[kaz7]

Looks fine except these:

llvm/lib/Target/VE/VVPISelLowering.cpp

85

Please follow above clang-format suggestion.

86

I'm not sure why it's safe to remove assert(LegalVecVT.isSimple()); here

[simoll]

Formatting

[simoll]

llvm/lib/Target/VE/VVPISelLowering.cpp

86

The assertion is still there. It's now in line 82.

[kaz7]

Thank you for answering my question. LGTM now.

llvm/lib/Target/VE/VECustomDAG.h

 #include "VEISelLowering.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
 
 namespace llvm {
 
 Optional<unsigned> getVVPOpcode(unsigned Opcode);
 
+bool isVVPUnaryOp(unsigned Opcode);
 bool isVVPBinaryOp(unsigned Opcode);
 bool isVVPReductionOp(unsigned Opcode);
 
 MVT splitVectorType(MVT VT);
 
 bool isPackedVectorType(EVT SomeVT);
 
 bool isMaskType(EVT SomeVT);

llvm/lib/Target/VE/VECustomDAG.cpp

bool isVVPOrVEC(unsigned Opcode) {
   case VEISD::VEC_BROADCAST:
 #define ADD_VVP_OP(VVPNAME, ...) case VEISD::VVPNAME:
 #include "VVPNodes.def"
     return true;
   }
   return false;
 }
 
+bool isVVPUnaryOp(unsigned VVPOpcode) {
+  switch (VVPOpcode) {
+#define ADD_UNARY_VVP_OP(VVPNAME, ...)                                         \
+  case VEISD::VVPNAME:                                                         \
+    return true;
+#include "VVPNodes.def"
+  }
+  return false;
+}
+
 bool isVVPBinaryOp(unsigned VVPOpcode) {
   switch (VVPOpcode) {
 #define ADD_BINARY_VVP_OP(VVPNAME, ...)                                        \
   case VEISD::VVPNAME:                                                         \
     return true;
 #include "VVPNodes.def"
   }
   return false;

llvm/lib/Target/VE/VVPISelLowering.cpp

SDValue VETargetLowering::lowerToVVP(SDValue Op, SelectionDAG &DAG) const {
   }
 
   // Materialize default mask and avl.
   if (!AVL)
     AVL = CDAG.getConstant(OpVecVT.getVectorNumElements(), MVT::i32);
   if (!Mask)
     Mask = CDAG.getConstantMask(Packing, true);
 
-  if (isVVPBinaryOp(VVPOpcode)) {
-    assert(LegalVecVT.isSimple());
+  if (isVVPUnaryOp(VVPOpcode))
+    return CDAG.getNode(VVPOpcode, LegalVecVT,
+                        {Op->getOperand(0), Mask, AVL});
+  if (isVVPBinaryOp(VVPOpcode))
     return CDAG.getNode(VVPOpcode, LegalVecVT,
                         {Op->getOperand(0), Op->getOperand(1), Mask, AVL});
-  }
   if (isVVPReductionOp(VVPOpcode)) {
     auto SrcHasStart = hasReductionStartParam(Op->getOpcode());
     SDValue StartV = SrcHasStart ? Op->getOperand(0) : SDValue();
     SDValue VectorV = Op->getOperand(SrcHasStart ? 1 : 0);
     return CDAG.getLegalReductionOpVVP(VVPOpcode, Op.getValueType(), StartV,
                                        VectorV, Mask, AVL, Op->getFlags());
   }
 

llvm/lib/Target/VE/VVPInstrInfo.td

 def SDTIntBinOpVVP : SDTypeProfile<1, 4, [     // vp_add, vp_and, etc.
   SDTCisSameAs<0, 1>,
   SDTCisSameAs<0, 2>,
   SDTCisInt<0>,
   SDTCisSameNumEltsAs<0, 3>,
   IsVLVT<4>
 ]>;
 
+// UnaryFPOp(x,mask,vl)
+def SDTFPUnaryOpVVP : SDTypeProfile<1, 3, [
+  SDTCisSameAs<0, 1>,
+  SDTCisFP<0>,
+  SDTCisInt<2>,
+  SDTCisSameNumEltsAs<0, 2>,
+  IsVLVT<3>
+]>;
+
 // BinaryFPOp(x,y,mask,vl)
 def SDTFPBinOpVVP : SDTypeProfile<1, 4, [      // vvp_fadd, etc.
   SDTCisSameAs<0, 1>,
   SDTCisSameAs<0, 2>,
   SDTCisFP<0>,
   SDTCisInt<3>,
   SDTCisSameNumEltsAs<0, 3>,
   IsVLVT<4>

 
 def vvp_xor    : SDNode<"VEISD::VVP_XOR",  SDTIntBinOpVVP>;
 def c_vvp_xor  : vvp_commutative<vvp_xor>;
 
 def vvp_srl    : SDNode<"VEISD::VVP_SRL",  SDTIntBinOpVVP>;
 def vvp_sra    : SDNode<"VEISD::VVP_SRA",  SDTIntBinOpVVP>;
 def vvp_shl    : SDNode<"VEISD::VVP_SHL",  SDTIntBinOpVVP>;
 
+def vvp_fneg    : SDNode<"VEISD::VVP_FNEG",  SDTFPUnaryOpVVP>;
+
 def vvp_fadd    : SDNode<"VEISD::VVP_FADD",  SDTFPBinOpVVP>;
 def c_vvp_fadd  : vvp_commutative<vvp_fadd>;
 def vvp_fsub    : SDNode<"VEISD::VVP_FSUB",  SDTFPBinOpVVP>;
 def vvp_fmul    : SDNode<"VEISD::VVP_FMUL",  SDTFPBinOpVVP>;
 def c_vvp_fmul  : vvp_commutative<vvp_fmul>;
 def vvp_fdiv    : SDNode<"VEISD::VVP_FDIV",  SDTFPBinOpVVP>;
 
 def vvp_ffma    : SDNode<"VEISD::VVP_FFMA",  SDTFPTernaryOpVVP>;

llvm/lib/Target/VE/VVPInstrPatternsVec.td

 }
 
 defm : VectorScatter<v256f64, v256i64, v256i1, "VSC">;
 defm : VectorScatter<v256i64, v256i64, v256i1, "VSC">;
 defm : VectorScatter<v256f32, v256i64, v256i1, "VSCU">;
 defm : VectorScatter<v256i32, v256i64, v256i1, "VSCL">;
 
 
+/// FNEG {
+// Directly modify the sign bit to flip the sign.
+
+// Set sign bits in a pack of <2 x f32>.
+def packed_fneg_imm     : OutPatFrag<(ins ),
+                          (i64 (SLLri (i64 (ORim 1, (i32 32))), 31))>;
+
+
+multiclass FNeg<ValueType DataVT> {
+  // Masked with select.
+  def : Pat<(vvp_select (vvp_fneg DataVT:$vx, (v256i1 srcvalue), (i32 srcvalue)),
+                        DataVT:$vfalse,
+                        v256i1:$mask,
+                        i32:$avl),
+            (VXORmvml_v (i32 1), $vx, $mask, $avl, $vfalse)>;
+
+  // Unmasked.
+  def : Pat<(vvp_fneg DataVT:$vx, (v256i1 true_mask), i32:$avl),
+            (VXORmvl (i32 1), $vx, $avl)>;
+
+  // Masked.
+  def : Pat<(vvp_fneg DataVT:$vx, v256i1:$mask, i32:$avl),
+            (VXORmvml (i32 1), $vx, $mask, $avl)>;
+}
+
+defm: FNeg<v256f32>;
+defm: FNeg<v256f64>;
+
+///// Packed FNeg /////
+
+// Masked with select.
+def : Pat<(vvp_select (vvp_fneg v512f32:$vx, (v512i1 srcvalue), (i32 srcvalue)),
+                      v512f32:$vfalse,
+                      v512i1:$mask,
+                      i32:$avl),
+          (v512f32 (PVXORrvml_v (packed_fneg_imm ), $vx, $mask, $avl, $vfalse))>;
+
+// Unmasked.
+def : Pat<(vvp_fneg v512f32:$vx, (v512i1 true_mask), i32:$avl),
+          (v512f32 (PVXORrvl (packed_fneg_imm ), $vx, $avl))>;
+
+// Masked.
+def : Pat<(vvp_fneg v512f32:$vx, v512i1:$mask, i32:$avl),
+          (v512f32 (PVXORrvml (packed_fneg_imm ), $vx, $mask, $avl))>;
+
+/// } FNEG
+
 multiclass Binary_rv<SDPatternOperator OpNode,
     ValueType ScalarVT, ValueType DataVT,
     ValueType MaskVT, string OpBaseName> {
   // Masked with passthru, broadcast.
   def : Pat<(vvp_select
                 (OpNode
                     (any_broadcast ScalarVT:$sx),
                     DataVT:$vy,

llvm/lib/Target/VE/VVPNodes.def

 
 /// ADD_VVP_OP(VVPNAME,SDNAME)
 /// \p VVPName is a VVP SDNode operator.
 /// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
 #ifndef ADD_VVP_OP
 #define ADD_VVP_OP(X, Y)
 #endif
 
+/// ADD_UNARY_VVP_OP(VVPNAME,SDNAME)
+/// \p VVPName is a VVP Unary operator.
+/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
+#ifndef ADD_UNARY_VVP_OP
+#define ADD_UNARY_VVP_OP(VVPNAME,SDNAME) \
+            ADD_VVP_OP(VVPNAME,SDNAME)
+#endif
+
 /// ADD_BINARY_VVP_OP(VVPNAME,SDNAME)
 /// \p VVPName is a VVP Binary operator.
 /// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
 #ifndef ADD_BINARY_VVP_OP
 #define ADD_BINARY_VVP_OP(VVPNAME,VPNAME,SDNAME) \
             ADD_VVP_OP(VVPNAME,SDNAME) \
             HANDLE_VP_TO_VVP(VPNAME, VVPNAME)
 #endif

 ADD_BINARY_VVP_OP(VVP_SRL,VP_LSHR,SRL) REGISTER_PACKED(VVP_SRL)
 ADD_BINARY_VVP_OP_COMPACT(SHL) REGISTER_PACKED(VVP_SHL)
 
 ADD_BINARY_VVP_OP_COMPACT(AND) REGISTER_PACKED(VVP_AND)
 ADD_BINARY_VVP_OP_COMPACT(OR)  REGISTER_PACKED(VVP_OR)
 ADD_BINARY_VVP_OP_COMPACT(XOR) REGISTER_PACKED(VVP_XOR)
 
 // FP arithmetic.
+ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)
 ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)
 ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)
 ADD_BINARY_VVP_OP_COMPACT(FMUL) REGISTER_PACKED(VVP_FMUL)
 ADD_BINARY_VVP_OP_COMPACT(FDIV)
 
 ADD_TERNARY_VVP_OP(VVP_FFMA,FMA) HANDLE_VP_TO_VVP(VP_FMA, VVP_FFMA) REGISTER_PACKED(VVP_FFMA)
 
 ADD_VVP_OP(VVP_SETCC, SETCC)
 
 // Shuffles.
 ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
 HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT)
 HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT)
 
 
 #undef ADD_BINARY_VVP_OP
 #undef ADD_TERNARY_VVP_OP
+#undef ADD_UNARY_VVP_OP
 #undef ADD_BINARY_VVP_OP_COMPACT
 #undef ADD_REDUCE_VVP_OP
 #undef ADD_VVP_OP
 #undef HANDLE_VP_TO_VVP
 #undef HANDLE_VVP_REDUCE_TO_SCALAR
 #undef REGISTER_PACKED

llvm/test/CodeGen/VE/Packed/vec_fneg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+define fastcc <512 x float> @test_vec_fneg_v512f32_v(<512 x float> %v) {
+; CHECK-LABEL: test_vec_fneg_v512f32_v:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or %s0, 1, (32)1
+; CHECK-NEXT:    sll %s0, %s0, 31
+; CHECK-NEXT:    lea %s1, 512
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    pvxor %v0, %s0, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %neg = fneg <512 x float> %v
+  ret <512 x float> %neg
+}

llvm/test/CodeGen/VE/Vector/vec_fneg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+
+define fastcc <256 x float> @test_vec_fneg_v256f32_v(<256 x float> %v) {
+; CHECK-LABEL: test_vec_fneg_v256f32_v:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vxor %v0, (1)1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %neg = fneg <256 x float> %v
+  ret <256 x float> %neg
+}
+
+define fastcc <256 x double> @test_vec_fneg_v256f64_v(<256 x double> %v) {
+; CHECK-LABEL: test_vec_fneg_v256f64_v:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vxor %v0, (1)1, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %neg = fneg <256 x double> %v
+  ret <256 x double> %neg
+}
+