[VE] Fix vmp0 subregister mapping

[simoll]

Summary

vmp0 is the all-ones v512i1 register and does not break down into subregisters.

[simoll]

Update test (invalid move to vm0 disappeared)

[kaz7]

LGTM.

llvm/lib/Target/VE/VERegisterInfo.td

 // Vector Index Register
 def VIX : VEVecReg<255, "vix", [], ["vix"]>;
 
 // Vector mask registers - 256 bits wide
 foreach I = 0-15 in
   def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>;
 
 // Aliases of VMs to use as a pair of two VM for packed instructions
+def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>;
+
 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
-foreach I = 0-7 in
+foreach I = 1-7 in
   def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I,
                         [!cast<VEMaskReg>("VM"#!shl(I,1)),
                          !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))],
                         ["vm"#!shl(I,1)]>;
 
 } // RegAltNameIndices = [AsmName]
 
 // Register classes.