Tweak/unify cl:opt flags for SSE register spilling.

[MatzeB]

Summary

WARNING: This is part of an experiment. The change is not ready for real review!

llvm/lib/CodeGen/InlineSpiller.cpp

 
 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
                                      cl::desc("Disable inline spill hoisting"));
 static cl::opt<bool>
 RestrictStatepointRemat("restrict-statepoint-remat",
                        cl::init(false), cl::Hidden,
                        cl::desc("Restrict remat for statepoint operands"));
 
-static cl::opt<bool> DisableSpillOtherClass("disable-spill-other-class",
-                                      cl::init(false), cl::Hidden,
-                                      cl::desc("Disable spilling to other register classes"));
-
 namespace {
 
 class HoistSpillHelper : private LiveRangeEdit::Delegate {
   MachineFunction &MF;
   LiveIntervals &LIS;
   LiveStacks &LSS;
   AliasAnalysis *AA;
   MachineDominatorTree &MDT;

 };
 
 } // end anonymous namespace
 
 Spiller::~Spiller() = default;
 
 void Spiller::anchor() {}
 
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
-                                   MachineFunction &mf,
+Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
+                                   MachineFunction &MF,
                                    VirtRegMap &VRM,
                                    const RegisterClassInfo &RegClassInfo,
                                    LiveRegMatrix &Matrix) {
   return new InlineSpiller(Pass, MF, VRM, RegClassInfo, Matrix);
 }
 
 //===----------------------------------------------------------------------===//
 //                                Snippets
void InlineSpiller::spillAll() {
   }
 
   // Delete all spilled registers.
   for (Register Reg : RegsToSpill)
     Edit->eraseVirtReg(Reg);
 }
 
 bool InlineSpiller::spillToOtherClass() {
-  if (DisableSpillOtherClass)
-    return false;
-
   const TargetRegisterClass* SpillRC = TRI.spillToOtherClass(MRI, Original);
   if (SpillRC == nullptr)
     return false;
 
   // Don't deal with subranges for now.
   for (Register Reg : RegsToSpill) {
     LiveInterval& LI = LIS.getInterval(Reg);
     if (LI.hasSubRanges()) {

llvm/lib/Target/X86/X86FrameLowering.cpp

bool X86FrameLowering::assignCalleeSavedSpillSlots(
 
   // Assign slots for GPRs. It increases frame size.
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i - 1].getReg();
 
     if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
       continue;
 
+    if (this->TRI->getSpillToSSE()) {
       // Try to spill to XMM register.
       if (Reg != X86::RBP && X86::GR64RegClass.contains(Reg) && !MF.callsUnwindInit()) {
         const MachineRegisterInfo &MRI = MF.getRegInfo();
         MCRegister SpillReg = MCRegister::NoRegister;
         for (unsigned NumRegs = X86::FR64RegClass.getNumRegs();
              lastUsedXmm < NumRegs; lastUsedXmm++) {
           MCRegister Candidate = X86::FR64RegClass.getRegister(lastUsedXmm);
           if (!MRI.isPhysRegUsed(Candidate)) {
             SpillReg = Candidate;
             lastUsedXmm++;
             break;
           }
         }
         if (SpillReg != MCRegister::NoRegister) {
           LLVM_DEBUG(dbgs() << "Save " << printReg(Reg, TRI)
                      << " by copy to " << printReg(SpillReg, TRI) << '\n');
           CSI[i - 1].setDstReg(SpillReg);
           continue;
         }
       }
+    }
 
     SpillSlotOffset -= SlotSize;
     CalleeSavedFrameSize += SlotSize;
 
     int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
     CSI[i - 1].setFrameIdx(SlotIndex);
   }
 

llvm/lib/Target/X86/X86RegisterInfo.h

private:
   ///
   unsigned FramePtr;
 
   /// BasePtr - X86 physical register used as a base ptr in complex stack
   /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
   /// variable size stack objects.
   unsigned BasePtr;
 
+  bool SpillToSSE;
+
 public:
   explicit X86RegisterInfo(const Triple &TT);
 
   // FIXME: This should be tablegen'd like getDwarfRegNum is
   int getSEHRegNum(unsigned i) const;
 
   /// getMatchingSuperRegClass - Return a subclass of the specified register
   /// class A so that each register in it has a sub-register of the
public:
   Register getBaseRegister() const { return BasePtr; }
   /// Returns physical register used as frame pointer.
   /// This will always returns the frame pointer register, contrary to
   /// getFrameRegister() which returns the "base pointer" in situations
   /// involving a stack, frame and base pointer.
   Register getFramePtr() const { return FramePtr; }
   // FIXME: Move to FrameInfok
   unsigned getSlotSize() const { return SlotSize; }
+  bool getSpillToSSE() const { return SpillToSSE; }
 
   bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
                              SmallVectorImpl<MCPhysReg> &Hints,
                              const MachineFunction &MF, const VirtRegMap *VRM,
                              const LiveRegMatrix *Matrix) const override;
 
   virtual const TargetRegisterClass* spillToOtherClass(const MachineRegisterInfo& MRI, Register Reg) const override;
 };
 
 } // End llvm namespace
 
 #endif

llvm/lib/Target/X86/X86RegisterInfo.cpp

 
 #define GET_REGINFO_TARGET_DESC
 #include "X86GenRegisterInfo.inc"
 
 static cl::opt<bool>
 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
           cl::desc("Enable use of a base pointer for complex stack frames"));
 
+static cl::opt<bool>
+EnableSpillToSSE("x86-spill-to-sse", cl::Hidden, cl::ZeroOrMore,
+          cl::desc("Enable spilling from GP to SSE registers"));
+
 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
                          X86_MC::getDwarfRegFlavour(TT, false),
                          X86_MC::getDwarfRegFlavour(TT, true),
-                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
+                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)),
+      SpillToSSE(EnableSpillToSSE) {
   X86_MC::initLLVMToSEHAndCVRegMapping(this);
 
   // Cache some information.
   Is64Bit = TT.isArch64Bit();
   IsWin64 = Is64Bit && TT.isOSWindows();
 
   // Use a callee-saved register as the base pointer.  These registers must
   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
LLVM_DEBUG({
     dbgs() << "\n";
   });
 #undef DEBUG_TYPE
 
   return true;
 }
 
 const TargetRegisterClass* X86RegisterInfo::spillToOtherClass(const MachineRegisterInfo& MRI, Register Reg) const {
+  if (!SpillToSSE)
+    return nullptr;
   unsigned RCId = MRI.getRegClass(Reg)->getID();
   // TODO: We should somehow compute a list of relevant classes
   // (all classes that only have RxX registers as members)
   switch (RCId) {
   case X86::GR32RegClassID:
   case X86::GR32_NOSPRegClassID:
   case X86::GR32_NOREXRegClassID:
   case X86::GR32_NOREX_NOSPRegClassID: