Add option to copy to SSE registers instead of push/pop in X86 prolog/epilog

[MatzeB]

Summary

WARNING: This is part of an experiment. It is NOT ready for real review/lading!

Add option to X86 prolog/epilog generation to copy values to SSE
registers instead of push/pop to stack when possible. This complements
the InlineSpiller changes to copy to SSE registers instead of spilling
(since prolog/epilog generation is a different code path).

llvm/lib/CodeGen/MachineCopyPropagation.cpp

for (MCRegister Reg : Defs)
       Tracker.clobberRegister(Reg, *TRI);
   }
 
   // If MBB doesn't have successors, delete the copies whose defs are not used.
   // If MBB does have successors, then conservative assume the defs are live-out
   // since we don't want to trust live-in lists.
   if (MBB.succ_empty()) {
     for (MachineInstr *MaybeDead : MaybeDeadCopies) {
+      // Skip COPYs used as part of FrameDestroy, since the code here just
+      // assumes nothing is live-out in a block without successors...
+      if (MaybeDead->getFlag(MachineInstr::FrameDestroy))
+        continue;
       LLVM_DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";
                  MaybeDead->dump());
       assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
 
       // Update matching debug values, if any.
       assert(MaybeDead->isCopy());
       Register SrcReg = MaybeDead->getOperand(1).getReg();
       MRI->updateDbgUsersToReg(SrcReg, CopyDbgUsers[MaybeDead]);

llvm/lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitCalleeSavedFrameMoves(
 
   // Add callee saved registers to move list.
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
   if (CSI.empty()) return;
 
   // Calculate offsets.
   for (std::vector<CalleeSavedInfo>::const_iterator
          I = CSI.begin(), E = CSI.end(); I != E; ++I) {
+    // TODO
+    if (I->isSpilledToReg())
+      continue;
+
     int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
     unsigned Reg = I->getReg();
     unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
 
     if (IsPrologue) {
       BuildCFI(MBB, MBBI, DL,
                MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
     } else {
void X86FrameLowering::emitPrologue(MachineFunction &MF,
   }
 
   // For EH funclets, only allocate enough space for outgoing calls. Save the
   // NumBytes value that we would've used for the parent frame.
   unsigned ParentFrameNumBytes = NumBytes;
   if (IsFunclet)
     NumBytes = getWinEHFuncletFrameSize(MF);
 
-  // Skip the callee-saved push instructions.
+  // Skip the callee-saved push and copy instructions.
   bool PushedRegs = false;
   int StackOffset = 2 * stackGrowth;
 
   while (MBBI != MBB.end() &&
-         MBBI->getFlag(MachineInstr::FrameSetup) &&
-         (MBBI->getOpcode() == X86::PUSH32r ||
-          MBBI->getOpcode() == X86::PUSH64r)) {
+         MBBI->getFlag(MachineInstr::FrameSetup)) {
+    unsigned Opcode = MBBI->getOpcode();
+    if (Opcode != X86::PUSH32r && Opcode != X86::PUSH64r &&
+        Opcode != TargetOpcode::COPY) {
+      break;
+    }
     PushedRegs = true;
     Register Reg = MBBI->getOperand(0).getReg();
     ++MBBI;
 
+    if (Opcode != TargetOpcode::COPY) {
       if (!HasFP && NeedsDwarfCFI) {
         // Mark callee-saved push instruction.
         // Define the current CFA rule to use the provided offset.
         assert(StackSize);
         BuildCFI(MBB, MBBI, DL,
                  MCCFIInstruction::cfiDefCfaOffset(nullptr, -StackOffset));
         StackOffset += stackGrowth;
       }
 
       if (NeedsWinCFI) {
         HasWinCFI = true;
         BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
             .addImm(Reg)
             .setMIFlag(MachineInstr::FrameSetup);
       }
     }
+  }
 
   // Realign stack after we pushed callee-saved registers (so that we'll be
   // able to calculate their offsets from the frame pointer).
   // Don't do this for Win64, it needs to realign the stack after the prologue.
   if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
     assert(HasFP && "There should be a frame pointer if stack is realigned.");
     BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
 
void X86FrameLowering::emitEpilogue(MachineFunction &MF,
   MachineBasicBlock::iterator FirstCSPop = MBBI;
   // Skip the callee-saved pop instructions.
   while (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PI = std::prev(MBBI);
     unsigned Opc = PI->getOpcode();
 
     if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
       if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
-          (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
+          (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
+          (Opc != TargetOpcode::COPY || !PI->getFlag(MachineInstr::FrameDestroy)))
         break;
       FirstCSPop = PI;
     }
 
     --MBBI;
   }
   MBBI = FirstCSPop;
 
if (hasFP(MF)) {
     for (unsigned i = 0; i < CSI.size(); ++i) {
       if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
         CSI.erase(CSI.begin() + i);
         break;
       }
     }
   }
 
+  unsigned lastUsedXmm = 0;
+
   // Assign slots for GPRs. It increases frame size.
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i - 1].getReg();
 
     if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
       continue;
 
+    // Try to spill to XMM register.
+    if (Reg != X86::RBP && X86::GR64RegClass.contains(Reg) && !MF.callsUnwindInit()) {
+      const MachineRegisterInfo &MRI = MF.getRegInfo();
+      MCRegister SpillReg = MCRegister::NoRegister;
+      for (unsigned NumRegs = X86::FR64RegClass.getNumRegs();
+           lastUsedXmm < NumRegs; lastUsedXmm++) {
+        MCRegister Candidate = X86::FR64RegClass.getRegister(lastUsedXmm);
+        if (!MRI.isPhysRegUsed(Candidate)) {
+          SpillReg = Candidate;
+          lastUsedXmm++;
+          break;
+        }
+      }
+      if (SpillReg != MCRegister::NoRegister) {
+        LLVM_DEBUG(dbgs() << "Save " << printReg(Reg, TRI)
+                   << " by copy to " << printReg(SpillReg, TRI) << '\n');
+        CSI[i - 1].setDstReg(SpillReg);
+        continue;
+      }
+    }
+
     SpillSlotOffset -= SlotSize;
     CalleeSavedFrameSize += SlotSize;
 
     int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
     CSI[i - 1].setFrameIdx(SlotIndex);
   }
 
   X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
bool X86FrameLowering::spillCalleeSavedRegisters(
   // for us, and there are no XMM CSRs on Win32.
   if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
     return true;
 
   // Push GPRs. It increases frame size.
   const MachineFunction &MF = *MBB.getParent();
   unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
   for (unsigned i = CSI.size(); i != 0; --i) {
-    unsigned Reg = CSI[i - 1].getReg();
+    const CalleeSavedInfo& CI = CSI[i - 1];
+    unsigned Reg = CI.getReg();
 
     if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
       continue;
 
     const MachineRegisterInfo &MRI = MF.getRegInfo();
     bool isLiveIn = MRI.isLiveIn(Reg);
     if (!isLiveIn)
       MBB.addLiveIn(Reg);
 
     // Decide whether we can add a kill flag to the use.
     bool CanKill = !isLiveIn;
     // Check if any subregister is live-in
     if (CanKill) {
       for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
         if (MRI.isLiveIn(*AReg)) {
           CanKill = false;
           break;
         }
       }
     }
 
+    if (CI.isSpilledToReg()) {
+      BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY),
+              CI.getDstReg())
+        .addReg(Reg, getKillRegState(CanKill))
+        .setMIFlag(MachineInstr::FrameSetup);
+      continue;
+    }
+
     // Do not set a kill flag on values that are also marked as live-in. This
     // happens with the @llvm-returnaddress intrinsic and with arguments
     // passed in callee saved registers.
     // Omitting the kill flags is conservatively correct even if the live-in
     // is not used after all.
     BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
       .setMIFlag(MachineInstr::FrameSetup);
   }
if (X86::VK16RegClass.contains(Reg))
       VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
 
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
     TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
   }
 
   // POP GPRs.
   unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
-  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
-    unsigned Reg = CSI[i].getReg();
+  for (const CalleeSavedInfo& CI : CSI) {
+    unsigned Reg = CI.getReg();
     if (!X86::GR64RegClass.contains(Reg) &&
         !X86::GR32RegClass.contains(Reg))
       continue;
 
+    if (CI.isSpilledToReg()) {
+      BuildMI(MBB, MI, DL, TII.get(TargetOpcode::COPY), Reg)
+        .addReg(CI.getDstReg(), RegState::Kill)
+        .setMIFlag(MachineInstr::FrameDestroy);
+      continue;
+    }
+
     BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
         .setMIFlag(MachineInstr::FrameDestroy);
   }
   return true;
 }
 
 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
                                             BitVector &SavedRegs,