[Hexagon] Use llvm::Register instead of unsigned in HexagonConstExtenders.cpp. NFC.

llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp

struct HexagonConstExtenders : public MachineFunctionPass {
     StringRef getPassName() const override {
       return "Hexagon constant-extender optimization";
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
 
   private:
     struct Register {
       Register() = default;
-      Register(unsigned R, unsigned S) : Reg(R), Sub(S) {}
+      Register(llvm::Register R, unsigned S) : Reg(R), Sub(S) {}
       Register(const MachineOperand &Op)
         : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
       Register &operator=(const MachineOperand &Op) {
         if (Op.isReg()) {
           Reg = Op.getReg();
           Sub = Op.getSubReg();
         } else if (Op.isFI()) {
           Reg = llvm::Register::index2StackSlot(Op.getIndex());
if (Ex.trivial()) {
         InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
                   .add(ExtOp)
                   .add(MachineOperand(Ex.Rs))
                   .addImm(Ex.S);
       } else {
         // No compounds are available. It is not clear whether we should
         // even process such extenders where the initializer cannot be
         // a single instruction, but do it for now.
-        unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
+        llvm::Register TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
         BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
           .add(MachineOperand(Ex.Rs))
           .addImm(Ex.S);
         if (Ex.Neg)
           InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
                     .add(ExtOp)
                     .add(MachineOperand(Register(TmpR, 0)));
         else