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Differential D117495

[VE] vp_select+vectorBinOp passthru isel and tests
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Authored by simoll on Jan 17 2022, 8:22 AM.

Details

Reviewers
kaz7
Commits
rG43994e9a4a83: [VE] vp_select+vectorBinOp passthru isel and tests
Summary

Extend the VE binaryop vector isel patterns to use passthru when the result of a SDNode is used in a vector select or merge.

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Event Timeline

simoll created this revision.Jan 17 2022, 8:22 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJan 17 2022, 8:22 AM
simoll requested review of this revision.Jan 17 2022, 8:22 AM
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Harbormaster completed remote builds in B143812: Diff 400561.Jan 17 2022, 9:02 AM
kaz7 accepted this revision.Jan 18 2022, 12:58 AM

LGTM

This revision is now accepted and ready to land.Jan 18 2022, 12:58 AM
This revision was landed with ongoing or failed builds.Jan 18 2022, 2:32 AM
Closed by commit rG43994e9a4a83: [VE] vp_select+vectorBinOp passthru isel and tests (authored by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rG43994e9a4a83: [VE] vp_select+vectorBinOp passthru isel and tests.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
53 lines
test/
CodeGen/
VE/
Vector/
89 lines
89 lines
89 lines
95 lines

Diff 400778

llvm/lib/Target/VE/VVPInstrPatternsVec.td

Show All 14 Lines
// VVP SDNode definitions. // VVP SDNode definitions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "VVPInstrInfo.td" include "VVPInstrInfo.td"
multiclass Binary_rv<SDPatternOperator OpNode, multiclass Binary_rv<SDPatternOperator OpNode,
ValueType ScalarVT, ValueType DataVT, ValueType ScalarVT, ValueType DataVT,
ValueType MaskVT, string OpBaseName> { ValueType MaskVT, string OpBaseName> {
// Masked with select, broadcast. // Masked with passthru, broadcast.
// TODO def : Pat<(vvp_select
(OpNode
(any_broadcast ScalarVT:$sx),
DataVT:$vy,
(MaskVT srcvalue),
(i32 srcvalue)),
DataVT:$vfalse,
MaskVT:$mask,
i32:$pivot),
(!cast<Instruction>(OpBaseName#"rvml_v")
ScalarVT:$sx,
$vy,
$mask,
$pivot,
$vfalse)>;
// Unmasked, broadcast. // Unmasked, broadcast.
def : Pat<(OpNode def : Pat<(OpNode
(any_broadcast ScalarVT:$sx), DataVT:$vy, (any_broadcast ScalarVT:$sx), DataVT:$vy,
(MaskVT true_mask), (MaskVT true_mask),
i32:$avl), i32:$avl),
(!cast<Instruction>(OpBaseName#"rvl") (!cast<Instruction>(OpBaseName#"rvl")
ScalarVT:$sx, $vy, $avl)>; ScalarVT:$sx, $vy, $avl)>;
// Masked, broadcast. // Masked, broadcast.
def : Pat<(OpNode def : Pat<(OpNode
(any_broadcast ScalarVT:$sx), DataVT:$vy, (any_broadcast ScalarVT:$sx), DataVT:$vy,
MaskVT:$mask, MaskVT:$mask,
i32:$avl), i32:$avl),
(!cast<Instruction>(OpBaseName#"rvml") (!cast<Instruction>(OpBaseName#"rvml")
ScalarVT:$sx, $vy, $mask, $avl)>; ScalarVT:$sx, $vy, $mask, $avl)>;
} }
multiclass Binary_vr<SDPatternOperator OpNode, multiclass Binary_vr<SDPatternOperator OpNode,
ValueType ScalarVT, ValueType DataVT, ValueType ScalarVT, ValueType DataVT,
ValueType MaskVT, string OpBaseName> { ValueType MaskVT, string OpBaseName> {
// Masked with select, broadcast. // Masked with passthru, broadcast.
// TODO def : Pat<(vvp_select
(OpNode
DataVT:$vx,
(any_broadcast ScalarVT:$sy),
(MaskVT srcvalue),
(i32 srcvalue)),
DataVT:$vfalse,
MaskVT:$mask,
i32:$pivot),
(!cast<Instruction>(OpBaseName#"vrml_v")
$vx,
ScalarVT:$sy,
$mask,
$pivot,
$vfalse)>;
// Unmasked, broadcast. // Unmasked, broadcast.
def : Pat<(OpNode def : Pat<(OpNode
DataVT:$vx, (any_broadcast ScalarVT:$sy), DataVT:$vx, (any_broadcast ScalarVT:$sy),
(MaskVT true_mask), (MaskVT true_mask),
i32:$avl), i32:$avl),
(!cast<Instruction>(OpBaseName#"vrl") (!cast<Instruction>(OpBaseName#"vrl")
$vx, ScalarVT:$sy, $avl)>; $vx, ScalarVT:$sy, $avl)>;
// Masked, broadcast. // Masked, broadcast.
def : Pat<(OpNode def : Pat<(OpNode
DataVT:$vx, (any_broadcast ScalarVT:$sy), DataVT:$vx, (any_broadcast ScalarVT:$sy),
MaskVT:$mask, MaskVT:$mask,
i32:$avl), i32:$avl),
(!cast<Instruction>(OpBaseName#"vrml") (!cast<Instruction>(OpBaseName#"vrml")
$vx, ScalarVT:$sy, $mask, $avl)>; $vx, ScalarVT:$sy, $mask, $avl)>;
} }
multiclass Binary_vv<SDPatternOperator OpNode, multiclass Binary_vv<SDPatternOperator OpNode,
ValueType DataVT, ValueType DataVT,
ValueType MaskVT, string OpBaseName> { ValueType MaskVT, string OpBaseName> {
// Masked with passthru, broadcast.
def : Pat<(vvp_select
(OpNode
DataVT:$vx,
DataVT:$vy,
(MaskVT srcvalue),
(i32 srcvalue)),
DataVT:$vfalse,
MaskVT:$mask,
i32:$pivot),
(!cast<Instruction>(OpBaseName#"vvml_v")
$vx,
$vy,
$mask,
$pivot,
$vfalse)>;
// Masked with select. // Masked with select.
// TODO // TODO
// Unmasked. // Unmasked.
def : Pat<(OpNode def : Pat<(OpNode
DataVT:$vx, DataVT:$vy, DataVT:$vx, DataVT:$vy,
(MaskVT true_mask), (MaskVT true_mask),
i32:$avl), i32:$avl),
▲ Show 20 Lines • Show All 151 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fadd.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
define fastcc <256 x float> @test_vp_fadd_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f32_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfadd.up %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fadd_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f32_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfadd.up %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %s0, i32 0
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fadd_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f32_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfadd.up %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %s1, i32 0
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
declare <256 x double> @llvm.vp.fadd.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
define fastcc <256 x double> @test_vp_fadd_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f64_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfadd.d %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fadd_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f64_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfadd.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x double> undef, double %s0, i32 0
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fadd_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fadd_v256f64_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfadd.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x double> undef, double %s1, i32 0
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}

llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fdiv.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
define fastcc <256 x float> @test_vp_fdiv_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f32_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfdiv.s %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fdiv_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f32_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfdiv.s %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %s0, i32 0
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fdiv_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f32_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfdiv.s %v0, %v1, %s0, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %s1, i32 0
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
declare <256 x double> @llvm.vp.fdiv.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
define fastcc <256 x double> @test_vp_fdiv_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f64_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfdiv.d %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fdiv_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f64_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfdiv.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x double> undef, double %s0, i32 0
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fdiv_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fdiv_v256f64_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfdiv.d %v0, %v1, %s0, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x double> undef, double %s1, i32 0
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}

llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fmul.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
define fastcc <256 x float> @test_vp_fmul_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f32_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfmul.up %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fmul_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f32_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfmul.up %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %s0, i32 0
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fmul_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f32_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfmul.up %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %s1, i32 0
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
declare <256 x double> @llvm.vp.fmul.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
define fastcc <256 x double> @test_vp_fmul_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f64_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfmul.d %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fmul_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f64_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfmul.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x double> undef, double %s0, i32 0
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fmul_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fmul_v256f64_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfmul.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x double> undef, double %s1, i32 0
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}

llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
define fastcc <256 x float> @test_vp_fsub_v256f32_vv_merge(<256 x float> %passthru, <256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f32_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvfsub.up %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fsub_v256f32_rv_merge(<256 x float> %passthru, float %s0, <256 x float> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f32_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfsub.up %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %s0, i32 0
%i0 = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
define fastcc <256 x float> @test_vp_fsub_v256f32_vr_merge(<256 x float> %passthru, <256 x float> %i0, float %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f32_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v2, %s0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: pvfsub.up %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %s1, i32 0
%i1 = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %passthru, i32 %n)
ret <256 x float> %r0
}
declare <256 x double> @llvm.vp.merge.v256f64(<256 x i1>, <256 x double>, <256 x double>, i32)
declare <256 x double> @llvm.vp.fsub.v256f64(<256 x double>, <256 x double>, <256 x i1>, i32)
define fastcc <256 x double> @test_vp_fsub_v256f64_vv_merge(<256 x double> %passthru, <256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f64_vv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfsub.d %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fsub_v256f64_rv_merge(<256 x double> %passthru, double %s0, <256 x double> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f64_rv_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfsub.d %v0, %s0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x double> undef, double %s0, i32 0
%i0 = shufflevector <256 x double> %xins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}
define fastcc <256 x double> @test_vp_fsub_v256f64_vr_merge(<256 x double> %passthru, <256 x double> %i0, double %s1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_fsub_v256f64_vr_merge:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vbrd %v2, %s0
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vfsub.d %v0, %v1, %v2, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x double> undef, double %s1, i32 0
%i1 = shufflevector <256 x double> %yins, <256 x double> undef, <256 x i32> zeroinitializer
%vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1> %m, i32 %n)
%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double> %passthru, i32 %n)
ret <256 x double> %r0
}