[AVR] Only push and clear R1 in interrupts when necessary

[aykevl]

Summary

r1 is a reserved register, but LLVM gives the APIs to know when it is used or not. So this patch uses these APIs to only save/clear/restore r1 in interrupts when necessary.

The main issue here was getting inline assembly to work. One could argue that this is the job of Clang, but for consistency I've made sure that r1 is always usable in inline assembly even if that means clearing it when it might not be needed.

Information on inline assembly in AVR can be found here:

https://www.nongnu.org/avr-libc/user-manual/inline_asm.html#asm_code

Essentially, this seems to suggest that r1 can be freely used in avr-gcc inline assembly, even without specifying it as an input operand.

---

This patch depends on D117425.

[aykevl]

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

1352

This was a bug.

llvm/lib/Target/AVR/AVRISelLowering.cpp

841

This is a bit of a hack, but I couldn't think of a better way.

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

863

I think the following form is more readable:

for (unsigned I = 0; I < N->getNumOperands(); I++) {
  SDValue Operand = N->getOperand(I);
  if (Operand.getValueType() == MVT::Glue)
    // The glue operand always needs to be at the end, so we need to treat it
    // specially.
    Glue = Operand;
  else
    Ops.push_back(Operand);
}

[benshi001]

This patch failed to be applied, so you need to rebase ?

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

841

I think this way is OK enough.

855

The flag of the implicit R1 register operand is better.

856

the implicit R1 register operand itself.

[aykevl]

@benshi001 I've rebased the patch and updated it with your suggestions.

[benshi001]

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

460 ↗

(On Diff #418203)

I am OK with current form. Just one more suggestion, you can add a new case of icall, current tests only contains a direct call but no indirect call. And you can add the icall test either in this patch or a new patch.

[benshi001]

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

460 ↗

(On Diff #418203)

I have debugged your code, and I find this line is unnecessary.

Since there is already such a line in AVRISelLowering.cpp / LowerCall():

// Add argument registers to the end of the list so that they are known live
// into the call.
for (auto Reg : RegsToPass) {
  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
}

// The R1 register must be passed as an implicit register so that R1 is
// correctly zeroed in interrupts.
Ops.push_back(DAG.getRegister(AVR::R1, MVT::i8));

That line in LowerCall is always executed, no matter direct call or indirect call, so the implicit R1 will be added twice for indirect calls.

[benshi001]

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

460 ↗

(On Diff #418203)

I still accept your patch, and you can delete this line in AVRDAGToDAGISel::select<AVRISD::CALL> when commit.

[benshi001]

llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

460 ↗

(On Diff #418203)

@aykevl , do you have any different opinion on my comments? I suggest you commit this ASAP.

[benshi001]

@avkevl, please commit this ASAP.

llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

buildMI(MBB, MBBI, OpShift)
       .addReg(DstReg, RegState::Kill);
 
   // Add the carry bit
   auto MIB = buildMI(MBB, MBBI, OpCarry)
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
                  .addReg(DstReg, getKillRegState(DstIsKill))
                  .addReg(ZERO_REGISTER);
 
-  // SREG is always implicitly killed
-  MIB->getOperand(2).setIsKill();
+  MIB->getOperand(3).setIsDead(); // SREG is always dead
+  MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
 
   MI.eraseFromParent();
   return true;
 }
 
 template <>
 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
   // In AVR, the rotate instructions behave quite unintuitively. They rotate

llvm/lib/Target/AVR/AVRFrameLowering.cpp

 
 void AVRFrameLowering::emitPrologue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator MBBI = MBB.begin();
   DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
   const AVRInstrInfo &TII = *STI.getInstrInfo();
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
   bool HasFP = hasFP(MF);
 
   // Interrupt handlers re-enable interrupts in function entry.
   if (AFI->isInterruptHandler()) {
     BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
         .addImm(0x07)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
   // handlers before saving any other registers.
   if (AFI->isInterruptOrSignalHandler()) {
-    BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
-        .addReg(AVR::R1R0, RegState::Kill)
+    BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
+        .addReg(AVR::R0, RegState::Kill)
         .setMIFlag(MachineInstr::FrameSetup);
 
     BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
         .addImm(STI.getIORegSREG())
         .setMIFlag(MachineInstr::FrameSetup);
     BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
         .addReg(AVR::R0, RegState::Kill)
         .setMIFlag(MachineInstr::FrameSetup);
+    if (!MRI.reg_empty(AVR::R1)) {
+      BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
+          .addReg(AVR::R1, RegState::Kill)
+          .setMIFlag(MachineInstr::FrameSetup);
       BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
           .addReg(AVR::R1, RegState::Define)
           .addReg(AVR::R1, RegState::Kill)
           .addReg(AVR::R1, RegState::Kill)
           .setMIFlag(MachineInstr::FrameSetup);
     }
+  }
 
   // Early exit if the frame pointer is not needed in this function.
   if (!HasFP) {
     return;
   }
 
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
void AVRFrameLowering::emitPrologue(MachineFunction &MF,
   // Write back R29R28 to SP and temporarily disable interrupts.
   BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
       .addReg(AVR::R29R28)
       .setMIFlag(MachineInstr::FrameSetup);
 }
 
 static void restoreStatusRegister(MachineFunction &MF, MachineBasicBlock &MBB) {
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
 
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
 
   DebugLoc DL = MBBI->getDebugLoc();
   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
   const AVRInstrInfo &TII = *STI.getInstrInfo();
 
   // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
   // handlers at the very end of the function, just before reti.
   if (AFI->isInterruptOrSignalHandler()) {
+    if (!MRI.reg_empty(AVR::R1)) {
+      BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R1);
+    }
     BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
     BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
         .addImm(STI.getIORegSREG())
         .addReg(AVR::R0, RegState::Kill);
-    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
+    BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
   }
 }
 
 void AVRFrameLowering::emitEpilogue(MachineFunction &MF,
                                     MachineBasicBlock &MBB) const {
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 
   // Early exit if the frame pointer is not needed in this function except for

llvm/lib/Target/AVR/AVRISelLowering.cpp

AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
   setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
   setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
 
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
 
+  setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
+
   for (MVT VT : MVT::integer_valuetypes()) {
     for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
       setLoadExtAction(N, VT, MVT::i1, Promote);
       setLoadExtAction(N, VT, MVT::i8, Expand);
     }
   }
 
   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
   // Vastart just stores the address of the VarArgsFrameIndex slot into the
   // memory location argument.
   SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
 
   return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
                       MachinePointerInfo(SV));
 }
 
+// Modify the existing ISD::INLINEASM node to add the implicit register r1.
+SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
+  SDValue R1Reg = DAG.getRegister(AVR::R1, MVT::i8);
+  if (Op.getOperand(Op.getNumOperands() - 1) == R1Reg ||
+      Op.getOperand(Op.getNumOperands() - 2) == R1Reg) {
+    // R1 has already been added. Don't add it again.
+    // If this isn't handled, we get called over and over again.
+    return Op;
+  }
+
+  // Get a list of operands to the new INLINEASM node. This is mostly a copy,
+  // with some edits.
+  // Add the following operands at the end (but before the glue node, if it's
+  // there):
+  //  - The flags of the implicit R1 register operand.
+  //  - The implicit R1 register operand itself.
+  SDLoc dl(Op);
+  SmallVector<SDValue, 8> Ops;
+  SDNode *N = Op.getNode();
+  SDValue Glue;
+  for (unsigned I = 0; I < N->getNumOperands(); I++) {
+    SDValue Operand = N->getOperand(I);
+    if (Operand.getValueType() == MVT::Glue) {
+      // The glue operand always needs to be at the end, so we need to treat it
+      // specially.
+      Glue = Operand;
+    } else {
+      Ops.push_back(Operand);
+    }
+  }
+  unsigned Flags = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
+  Ops.push_back(DAG.getTargetConstant(Flags, dl, MVT::i32));
+  Ops.push_back(R1Reg);
+  if (Glue) {
+    Ops.push_back(Glue);
+  }
+
+  // Replace the current INLINEASM node with a new one that has R1 as implicit
+  // parameter.
+  SDValue New = DAG.getNode(N->getOpcode(), dl, N->getVTList(), Ops);
+  DAG.ReplaceAllUsesOfValueWith(Op, New);
+  DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), New.getValue(1));
+
+  return New;
+}
+
 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default:
     llvm_unreachable("Don't know how to custom lower this!");
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
   case ISD::ROTL:
case ISD::SELECT_CC:
     return LowerSELECT_CC(Op, DAG);
   case ISD::SETCC:
     return LowerSETCC(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
   case ISD::SDIVREM:
   case ISD::UDIVREM:
     return LowerDivRem(Op, DAG);
+  case ISD::INLINEASM:
+    return LowerINLINEASM(Op, DAG);
   }
 
   return SDValue();
 }
 
 /// Replace a node with an illegal result type
 /// with a new node built out of custom code.
 void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are known live
   // into the call.
   for (auto Reg : RegsToPass) {
     Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
   }
 
+  // The R1 register must be passed as an implicit register so that R1 is
+  // correctly zeroed in interrupts.
+  Ops.push_back(DAG.getRegister(AVR::R1, MVT::i8));
+
   // Add a register mask operand representing the call-preserved registers.
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   const uint32_t *Mask =
       TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
   assert(Mask && "Missing call preserved mask for calling convention");
   Ops.push_back(DAG.getRegisterMask(Mask));
 
   if (InFlag.getNode()) {
AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   // Don't emit the ret/reti instruction when the naked attribute is present in
   // the function being compiled.
   if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) {
     return Chain;
   }
 
   const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
 
+  if (!AFI->isInterruptOrSignalHandler()) {
+    // The return instruction has an implicit R1 operand: it must contain zero
+    // on return.
+    // This is not needed in interrupts however, where R1 is handled specially
+    // (only pushed/popped when needed).
+    RetOps.push_back(DAG.getRegister(AVR::R1, MVT::i8));
+  }
+
   unsigned RetOpc =
       AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG;
 
   RetOps[0] = Chain; // Update chain.
 
   if (Flag.getNode()) {
     RetOps.push_back(Flag);
   }

llvm/lib/Target/AVR/AVRInstrInfo.td

def NEGRd
                          (implicit SREG)]>;
 
   // NEGW Rd+1:Rd
   //
   // Expands to:
   // neg Rd+1
   // neg Rd
   // sbc Rd+1, r1
+  let Uses = [R1] in
   def NEGWRd : Pseudo<(outs DREGS
                        : $rd),
                       (ins DREGS
                        : $src),
                       "negw\t$rd",
                       [(set i16
                         : $rd, (ineg i16
                                 : $src)),
def ASRWRd : Pseudo<(outs DREGS
                       [(set i16
                         : $rd, (AVRasr i16
                                 : $src)),
                        (implicit SREG)]>;
 
   def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd",
                         [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>;
 
+  let Uses = [R1] in
   def ROLBRd : Pseudo<(outs GPR8
                        : $rd),
                       (ins GPR8
                        : $src),
                       "rolb\t$rd",
                       [(set i8
                         : $rd, (AVRrol i8
                                 : $src)),

llvm/test/CodeGen/AVR/interrupts.ll

 ; RUN: llc < %s -march=avr | FileCheck %s
 
 @count = global i8 0
+@funcptr = global void () addrspace(1)* null
 
 define avr_intrcc void @interrupt_handler() {
 ; CHECK-LABEL: interrupt_handler:
 ; CHECK: sei
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   ret void
 }
 
 define void @interrupt_handler_via_ir_attribute() #0 {
 ; CHECK-LABEL: interrupt_handler_via_ir_attribute:
 ; CHECK: sei
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   ret void
 }
 
 define avr_signalcc void @signal_handler() {
 ; CHECK-LABEL: signal_handler:
 ; CHECK-NOT: sei
 ; CHECK: push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   ret void
 }
 
 define void @signal_handler_via_attribute() #1 {
 ; CHECK-LABEL: signal_handler_via_attribute:
 ; CHECK-NOT: sei
 ; CHECK: push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   ret void
 }
 
 define avr_intrcc void @interrupt_alloca() {
 ; CHECK-LABEL: interrupt_alloca:
 ; CHECK: sei
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK: push r28
 ; CHECK-NEXT: push r29
 ; CHECK-NEXT: in r28, 61
 ; CHECK-NEXT: in r29, 62
 ; CHECK-NEXT: sbiw r28, 1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, r29
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: out 61, r28
 ; CHECK: adiw r28, 1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: cli
 ; CHECK-NEXT: out 62, r29
 ; CHECK-NEXT: out 63, r0
 ; CHECK-NEXT: out 61, r28
 ; CHECK-NEXT: pop r29
 ; CHECK-NEXT: pop r28
 ; CHECK: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   alloca i8
   ret void
 }
 
 define void @signal_handler_with_increment() #1 {
 ; CHECK-LABEL: signal_handler_with_increment:
 ; CHECK:      push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
-; CHECK-NEXT: clr r1
 ; CHECK-NEXT: push r24
 ; CHECK-NEXT: lds r24, count
 ; CHECK-NEXT: inc r24
 ; CHECK-NEXT: sts count, r24
 ; CHECK-NEXT: pop r24
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   %old = load volatile i8, i8* @count
   %new = add i8 %old, 1
   store volatile i8 %new, i8* @count
   ret void
 }
 
+; Check that r1 is saved/restored and set to 0 when using inline assembly.
+define void @signal_handler_with_asm() #1 {
+; CHECK-LABEL: signal_handler_with_asm:
+; CHECK:      push r0
+; CHECK-NEXT: in r0, 63
+; CHECK-NEXT: push r0
+; CHECK-NEXT: push r1
+; CHECK-NEXT: clr r1
+; CHECK-NEXT: push r24
+; CHECK-NEXT: ldi
+;             ;APP
+; CHECK:      mov
+;             ;NO_APP
+; CHECK:      pop r24
+; CHECK-NEXT: pop r1
+; CHECK-NEXT: pop r0
+; CHECK-NEXT: out 63, r0
+; CHECK-NEXT: pop r0
+; CHECK-NEXT: reti
+  call i8 asm sideeffect "mov $0, $1", "=r,r"(i8 3) nounwind
+  ret void
+}
+
 declare void @foo()
 
 ; When a signal handler calls a function, it must push/pop all call clobbered
 ; registers.
 define void @signal_handler_with_call() #1 {
 ; CHECK-LABEL: signal_handler_with_call:
 ; CHECK:      push r0
-; CHECK-NEXT: push r1
 ; CHECK-NEXT: in r0, 63
 ; CHECK-NEXT: push r0
+; CHECK-NEXT: push r1
 ; CHECK-NEXT: clr r1
 ; CHECK-NEXT: push r18
 ; CHECK-NEXT: push r19
 ; CHECK-NEXT: push r20
 ; CHECK-NEXT: push r21
 ; CHECK-NEXT: push r22
 ; CHECK-NEXT: push r23
 ; CHECK-NEXT: push r24

 ; CHECK-NEXT: pop r25
 ; CHECK-NEXT: pop r24
 ; CHECK-NEXT: pop r23
 ; CHECK-NEXT: pop r22
 ; CHECK-NEXT: pop r21
 ; CHECK-NEXT: pop r20
 ; CHECK-NEXT: pop r19
 ; CHECK-NEXT: pop r18
+; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: out 63, r0
-; CHECK-NEXT: pop r1
 ; CHECK-NEXT: pop r0
 ; CHECK-NEXT: reti
   call void @foo()
   ret void
 }
 
+define void @signal_handler_with_icall() #1 {
+; CHECK-LABEL: signal_handler_with_icall:
+; CHECK:      push    r0
+; CHECK-NEXT: in      r0, 63
+; CHECK-NEXT: push    r0
+; CHECK-NEXT: push    r1
+; CHECK-NEXT: clr     r1
+; CHECK-NEXT: push    r18
+; CHECK-NEXT: push    r19
+; CHECK-NEXT: push    r20
+; CHECK-NEXT: push    r21
+; CHECK-NEXT: push    r22
+; CHECK-NEXT: push    r23
+; CHECK-NEXT: push    r24
+; CHECK-NEXT: push    r25
+; CHECK-NEXT: push    r26
+; CHECK-NEXT: push    r27
+; CHECK-NEXT: push    r30
+; CHECK-NEXT: push    r31
+; CHECK-NEXT: lds     r30, funcptr
+; CHECK-NEXT: lds     r31, funcptr+1
+; CHECK-NEXT: icall
+; CHECK-NEXT: pop     r31
+; CHECK-NEXT: pop     r30
+; CHECK-NEXT: pop     r27
+; CHECK-NEXT: pop     r26
+; CHECK-NEXT: pop     r25
+; CHECK-NEXT: pop     r24
+; CHECK-NEXT: pop     r23
+; CHECK-NEXT: pop     r22
+; CHECK-NEXT: pop     r21
+; CHECK-NEXT: pop     r20
+; CHECK-NEXT: pop     r19
+; CHECK-NEXT: pop     r18
+; CHECK-NEXT: pop     r1
+; CHECK-NEXT: pop     r0
+; CHECK-NEXT: out     63, r0
+; CHECK-NEXT: pop     r0
+; CHECK-NEXT: reti
+  %ptr = load volatile void() addrspace(1)*, void() addrspace(1)** @funcptr
+  call void %ptr()
+  ret void
+}
+
 attributes #0 = { "interrupt" }
 attributes #1 = { "signal" }

llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir

bb.0.entry:
     liveins: $r15r14
 
     ; CHECK-LABEL: test_negwrd
 
     ; CHECK:      $r15 = NEGRd killed $r15, implicit-def dead $sreg
     ; CHECK-NEXT: $r14 = NEGRd $r14
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
 
-    $r15r14 = NEGWRd $r15r14, implicit-def $sreg
+    $r15r14 = NEGWRd $r15r14, implicit-def $sreg, implicit $r1
 ...

llvm/test/CodeGen/AVR/pseudo/ROLBrd.mir

+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+# This test checks the expansion of the 8-bit ROLB (rotate) pseudo instruction.
+
+--- |
+  target triple = "avr--"
+  define void @test_rolbrd() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test_rolbrd
+body: |
+  bb.0.entry:
+    liveins: $r14
+
+    ; CHECK-LABEL: test_rolbrd
+
+    ; CHECK:      $r14 = ADDRdRr killed $r14, killed $r14, implicit-def $sreg
+    ; CHECK-NEXT: $r14 = ADCRdRr $r14, $r1, implicit-def dead $sreg, implicit killed $sreg
+
+    $r14 = ROLBRd $r14, implicit-def $sreg, implicit $r1
+...

llvm/test/CodeGen/AVR/zeroreg.ll

+; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
+
+; This file tests whether the compiler correctly works with the r1 register,
+; clearing it when needed.
+
+; Test regular use of r1 as a zero register.
+; CHECK-LABEL: store8zero:
+; CHECK:      st {{[XYZ]}}, r1
+; CHECK-NEXT: mov r24, r1
+; CHECK-NEXT: ret
+define i8 @store8zero(i8* %x) {
+  store i8 0, i8* %x
+  ret i8 0
+}
+
+; Test that mulitplication instructions (mul, muls, etc) clobber r1 and require
+; a "clr r1" instruction.
+; CHECK-LABEL: mul:
+; CHECK:      muls
+; CHECK-NEXT: clr r1
+; CHECK-NEXT: st {{[XYZ]}}, r0
+; CHECK-NEXT: ret
+define void @mul(i8* %ptr, i8 %n) {
+  %result = mul i8 %n, 3
+  store i8 %result, i8* %ptr
+  ret void
+}