[AVR] Make use of the constant value 0 in R1

[aykevl]

Summary

The register r1 is defined to have the constant value 0 in the avr-gcc calling convention (which we follow). Unfortunately, we don't really make use of it. This patch replaces LDI 0 instructions with a copy from r1.

This reduces code size: my AVR build of compiler-rt goes from 50660 to 50240 bytes of code size, which is a 0.8% reduction. Presumably it will also improve execution speed, although I didn't measure this.

---

This patch took me a looong time, with many failed attempts. Finally I have something that works. It can still be improved, but that can happen in follow up patches. A 0.8% decrease in code size is already pretty significant.

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1699

I think we need to check the device family, AFAIK, r17 is used as zero_reg on avr-tiny family.

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1699

do we need to make a helper function int getRegZero(void) in AVRSubtarget.h, just like I have done as getIORegRAMPZ(void) ? The new helper function will return r17 for avr-tiny devices.

[aykevl]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1699

You are correct. However, there are many other places in the compiler that assume R1 is the zero register (and R0 is the scratch register). For example, here:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AVR/AVRRegisterInfo.cpp#L53-L57
I agree we should use R16 and R17 for avr-tiny, but I would prefer to do that all in once patch. I can do that after this patch and D117725 have landed? What do you think?

[benshi001]

llvm/lib/Target/AVR/AVRISelLowering.cpp

1699

I agree with you. Actually I am planing and investigating implementation of avttiny.

llvm/lib/Target/AVR/AVRISelLowering.h

SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                           SmallVectorImpl<SDValue> &InVals) const;
 
 protected:
   const AVRSubtarget &Subtarget;
 
 private:
   MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
   MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
+  MachineBasicBlock *insertCopyR1(MachineInstr &MI,
+                                  MachineBasicBlock *BB) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_ISEL_LOWERING_H

llvm/lib/Target/AVR/AVRISelLowering.cpp

MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
   if (isCopyMulResult(I))
     ++I;
   BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
       .addReg(AVR::R1)
       .addReg(AVR::R1);
   return BB;
 }
 
+// Insert a read from R1, which almost always contains the value 0.
+MachineBasicBlock *
+AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const {
+  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
+  MachineBasicBlock::iterator I(MI);
+  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY))
+      .add(MI.getOperand(0))
+      .addReg(AVR::R1);
+  MI.eraseFromParent();
+  return BB;
+}
+
 MachineBasicBlock *
 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                MachineBasicBlock *MBB) const {
   int Opc = MI.getOpcode();
 
   // Pseudo shift instructions with a non constant shift amount are expanded
   // into a loop.
   switch (Opc) {
   case AVR::Lsl8:
   case AVR::Lsl16:
   case AVR::Lsr8:
   case AVR::Lsr16:
   case AVR::Rol8:
   case AVR::Rol16:
   case AVR::Ror8:
   case AVR::Ror16:
   case AVR::Asr8:
   case AVR::Asr16:
     return insertShift(MI, MBB);
   case AVR::MULRdRr:
   case AVR::MULSRdRr:
     return insertMul(MI, MBB);
+  case AVR::CopyR1:
+    return insertCopyR1(MI, MBB);
   }
 
   assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
          "Unexpected instr type to insert");
 
   const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
                                 ->getParent()
                                 ->getSubtarget()

llvm/lib/Target/AVR/AVRInstrInfo.td

def Asr16 : ShiftPseudo<(outs DREGS
                         (ins DREGS
                          : $src, GPR8
                          : $cnt),
                         "# Asr16 PSEUDO", [(set i16
                                             : $dst, (AVRasrLoop i16
                                                      : $src, i8
                                                      : $cnt))]>;
 
+// lowered to a copy from R1, which contains the value zero.
+let usesCustomInserter=1 in
+def CopyR1 : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
+
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //===----------------------------------------------------------------------===//
 
 //: TODO: look in x86InstrCompiler.td for odd encoding trick related to
 // add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor)
 
 // the add instruction always writes the carry flag

llvm/test/CodeGen/AVR/smul-with-overflow.ll

 ; CHECK: muls   r24, r22
 ; CHECK: mov    [[HIGH:r[0-9]+]], r1
 ; CHECK: mov    [[LOW:r[0-9]+]], r0
 ; CHECK: lsl    {{.*}}[[LOW]]
 ; CHECK: sbc    {{.*}}[[LOW]], {{.*}}[[LOW]]
 ; CHECK: ldi    [[RET:r[0-9]+]], 1
 ; CHECK: cp     {{.*}}[[HIGH]], {{.*}}[[LOW]]
 ; CHECK: brne   [[LABEL:.LBB[_0-9]+]]
-; CHECK: ldi    {{.*}}[[RET]], 0
+; CHECK: mov    {{.*}}[[RET]], r1
 ; CHECK: {{.*}}[[LABEL]]
 ; CHECK: ret
 }
 
 declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8)

llvm/test/CodeGen/AVR/store-undef.ll

 ; RUN: llc < %s -march=avr | FileCheck %s
 
 ; This test checks that we can successfully lower a store
 ; to an undefined pointer.
 
 ; CHECK-LABEL: foo
 define void @foo() {
 
-  ; CHECK:      ldi [[SRC:r[0-9]+]], 0
-  ; CHECK-NEXT: st [[PTRREG:X|Y|Z]], [[SRC]]
+  ; CHECK: st [[PTRREG:X|Y|Z]], r1
   store i8 0, i8* undef, align 4
   ret void
 }

llvm/test/CodeGen/AVR/umul-with-overflow.ll

 ; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
 
 define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
 ; CHECK-LABEL: unsigned_multiplication_did_overflow:
 entry-block:
   %2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1)
   %3 = extractvalue { i8, i1 } %2, 1
   ret i1 %3
 
 ; Multiply, return if the high byte is zero
 ;
 ; CHECK: mul    r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: mov    [[HIGH:r[0-9]+]], r1
 ; CHECK: ldi    [[RET:r[0-9]+]], 1
 ; CHECK: cpi    {{.*}}[[HIGH]], 0
 ; CHECK: brne   [[LABEL:.LBB[_0-9]+]]
-; CHECK: ldi    {{.*}}[[RET]], 0
+; CHECK: mov    {{.*}}[[RET]], r1
 ; CHECK: {{.*}}[[LABEL]]
 ; CHECK: ret
 }
 
 declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8)