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Differential D11631

[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
ClosedPublic

Authored by hvarga on Jul 30 2015, 12:12 AM.

Details

Reviewers
dsanders
zbuljan
zoran.jovanovic
Commits
rL250377: [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Summary

The patch implements microMIPS LWLE, LWRE, SWLE and SWRE instructions.

Diff Detail

Event Timeline

hvarga updated this revision to Diff 31000.Jul 30 2015, 12:12 AM
hvarga retitled this revision from to [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions.
hvarga updated this object.
hvarga added reviewers: zoran.jovanovic, zbuljan, dsanders.
hvarga added subscribers: petarj, llvm-commits.
dsanders accepted this revision.Sep 14 2015, 7:13 AM
dsanders edited edge metadata.

LGTM with some nits

lib/Target/Mips/Disassembler/MipsDisassembler.cpp
288–290

Indentation

lib/Target/Mips/MicroMipsInstrFormats.td
405

Naming convention: Should begin with POOL32C_

407

Assign to 'base' and 'offset' to make special encoding self documenting

lib/Target/Mips/MicroMipsInstrInfo.td
717–726

Indentation

This revision is now accepted and ready to land.Sep 14 2015, 7:13 AM
Closed by commit rL250377: [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions (authored by hvarga). · Explain WhyOct 15 2015, 12:25 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
23 lines
14 lines
10 lines
test/
MC/
Disassembler/
Mips/
8 lines
8 lines
Mips/
12 lines
mips32r6/
9 lines
mips64r6/
8 lines
8 lines

Diff 31000

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
dsandersUnsubmitted
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Indentation

dsanders: Indentation
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
▲ Show 20 Lines • Show All 1,003 Lines • ▼ Show 20 Lines if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
return MCDisassembler::Fail; return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Mips::SP)); Inst.addOperand(MCOperand::createReg(Mips::SP));
Inst.addOperand(MCOperand::createImm(Offset << 2)); Inst.addOperand(MCOperand::createImm(Offset << 2));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0x1ff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::createReg(Reg));
Inst.addOperand(MCOperand::createReg(Base));
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int Offset = SignExtend32<12>(Insn & 0x0fff); int Offset = SignExtend32<12>(Insn & 0x0fff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5); unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5); unsigned Base = fieldFromInstruction(Insn, 16, 5);
▲ Show 20 Lines • Show All 564 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 396 Lines • ▼ Show 20 Linesclass LWL_FM_MM<bits<4> funct> {
let Inst{31-26} = 0x18; let Inst{31-26} = 0x18;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16}; let Inst{20-16} = addr{20-16};
let Inst{15-12} = funct; let Inst{15-12} = funct;
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
} }
class STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
dsandersUnsubmitted
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Naming convention: Should begin with POOL32C_

dsanders: Naming convention: Should begin with POOL32C_
bits<5> rt;
bits<21> addr;
dsandersUnsubmitted
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Assign to 'base' and 'offset' to make special encoding self documenting

dsanders: Assign to 'base' and 'offset' to make special encoding self documenting
bits<32> Inst;
let Inst{31-26} = 0x18;
let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16};
let Inst{15-12} = type;
let Inst{11-9} = funct;
let Inst{8-0} = addr{8-0};
}
class CMov_F_I_FM_MM<bits<7> func> : MMArch { class CMov_F_I_FM_MM<bits<7> func> : MMArch {
bits<5> rd; bits<5> rd;
bits<5> rs; bits<5> rs;
bits<3> fcc; bits<3> fcc;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x15; let Inst{31-26} = 0x15;
▲ Show 20 Lines • Show All 533 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 708 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x0>; LWL_FM_MM<0x0>;
def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>, def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x1>; LWL_FM_MM<0x1>;
def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>, def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x8>; LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>; LWL_FM_MM<0x9>;
let DecoderMethod = "DecodeMemMMImm9" in {
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0x6, 0x2>;
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0x6, 0x3>;
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0xa, 0x0>;
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
}
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Indentation

dsanders: Indentation
/// Load and Store Instructions - multiple /// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>; def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>; def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
/// Load and Store Pair Instructions /// Load and Store Pair Instructions
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips.txt

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
0x46 0xce # CHECK: sdbbp16 14 0x46 0xce # CHECK: sdbbp16 14
0x84 0x34 # CHECK: movep $5, $6, $2, $3 0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x00 0x57 0x7c # CHECK: ei
0x00 0x0a 0x57 0x7c # CHECK: ei $10 0x00 0x0a 0x57 0x7c # CHECK: ei $10
0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)

test/MC/Disassembler/Mips/micromips_le.txt

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Lines
0xce 0x46 # CHECK: sdbbp16 14 0xce 0x46 # CHECK: sdbbp16 14
0x34 0x84 # CHECK: movep $5, $6, $2, $3 0x34 0x84 # CHECK: movep $5, $6, $2, $3
0x00 0x00 0x7c 0x57 # CHECK: ei 0x00 0x00 0x7c 0x57 # CHECK: ei
0x0a 0x00 0x7c 0x57 # CHECK: ei $10 0x0a 0x00 0x7c 0x57 # CHECK: ei $10
0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)

test/MC/Mips/micromips-control-instructions.s

Show All 33 Lines
# CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57] # CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57]
# CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57] # CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57]
# CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93] # CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93]
# CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93] # CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93]
# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03] # CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03]
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Big endian # Big endian
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c] # CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
# CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c] # CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
# CHECK-EB: .set push # CHECK-EB: .set push
# CHECK-EB: .set mips32r2 # CHECK-EB: .set mips32r2
# CHECK-EB: rdhwr $5, $29 # CHECK-EB: rdhwr $5, $29
Show All 17 Lines
# CHECK-EB: ei # encoding: [0x00,0x00,0x57,0x7c] # CHECK-EB: ei # encoding: [0x00,0x00,0x57,0x7c]
# CHECK-EB: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] # CHECK-EB: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
# CHECK-EB: wait # encoding: [0x00,0x00,0x93,0x7c] # CHECK-EB: wait # encoding: [0x00,0x00,0x93,0x7c]
# CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c] # CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
# CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c] # CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c]
# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
sdbbp sdbbp
sdbbp 34 sdbbp 34
rdhwr $5, $29 rdhwr $5, $29
cache 1, 8($5) cache 1, 8($5)
pref 1, 8($5) pref 1, 8($5)
ssnop ssnop
ehb ehb
Show All 12 Lines# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
ei $0 ei $0
ei $10 ei $10
wait wait
wait 17 wait 17
tlbp tlbp
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr
swre $24, 5($3)
swle $24, 5($3)
lwre $24, 5($3)
lwle $24, 2($4)

test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s

Show All 11 Lines .set noat
ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction