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[AMDGPU] Enable divergence predicates for ctlz/cttz
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Authored by alex-t on Dec 20 2021, 8:10 AM.

Details

Summary

ctlz/cttz get lowered to the set of target opcodes
This change enables the ISel to select SALU or VALU form according to the SDNode divergence.
CTLZ - S_FLBIT_I32_B32 if uniform and V_FFBH_U32_e64 if divergent
CTTZ - S_FF1_I32_B32 if uniform and V_FFBL_B32_e64 if divergent
Also @llvm.amdgcn.sffbh.i32 gets lowered to S_FLBIT_I32 if uniform and V_FFBH_I32_e64 if divergent

NOTE: 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B64 are not currently supported by the DAG ISel. ctlz/cttz with i64 input are split into two 32bit instructions. Nevertheless, they already have the patterns and were equipped with the divergence predicates to make sure they will be selected correctly when enabled.

Diff Detail

Event Timeline

alex-t created this revision.Dec 20 2021, 8:10 AM
alex-t requested review of this revision.Dec 20 2021, 8:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 20 2021, 8:10 AM
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alex-t edited the summary of this revision. (Show Details)Dec 20 2021, 8:12 AM
foad added a comment.Dec 20 2021, 8:13 AM

Typo in subject line "devergence"

alex-t edited the summary of this revision. (Show Details)Dec 20 2021, 8:14 AM
alex-t edited the summary of this revision. (Show Details)
alex-t retitled this revision from [AMDGPU] Enable devergence predicates for ctlz/cttz to [AMDGPU] Enable divergence predicates for ctlz/cttz.
foad added a comment.Dec 20 2021, 8:16 AM

New test file should not be executable and needs a newline at the end.

alex-t updated this revision to Diff 395464.Dec 20 2021, 8:28 AM

test corrected

rampitec accepted this revision.Dec 20 2021, 9:21 AM
This revision is now accepted and ready to land.Dec 20 2021, 9:21 AM
This revision was landed with ongoing or failed builds.Dec 20 2021, 9:51 AM
This revision was automatically updated to reflect the committed changes.