[InstCombine] Allow fake vector insert folding to bit-logic only if the insert element is integer type

[Srividya-Karumuri]

Summary

The below commit is causing assertion when insert element type is not integer
type such as half. This is because the transformation is creating zext before
doing bitwise OR, and the zext is supported only for integer types
https://github.com/llvm/llvm-project/commit/80ab06c599a0f5a90951c36a57b2a9b492b19d61

[spatel]

LGTM - thanks for the fix!

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

if (FixedVectorType *SrcVTy = dyn_cast<FixedVectorType>(SrcTy)) {
 
     // Convert an artificial vector insert into more analyzable bitwise logic.
     unsigned BitWidth = DestTy->getScalarSizeInBits();
     Value *X, *Y;
     uint64_t IndexC;
     if (match(Src, m_OneUse(m_InsertElt(m_OneUse(m_BitCast(m_Value(X))),
                                         m_Value(Y), m_ConstantInt(IndexC)))) &&
         DestTy->isIntegerTy() && X->getType() == DestTy &&
-        isDesirableIntType(BitWidth)) {
+        Y->getType()->isIntegerTy() && isDesirableIntType(BitWidth)) {
       // Adjust for big endian - the LSBs are at the high index.
       if (DL.isBigEndian())
         IndexC = SrcVTy->getNumElements() - 1 - IndexC;
 
       // We only handle (endian-normalized) insert to index 0. Any other insert
       // would require a left-shift, so that is an extra instruction.
       if (IndexC == 0) {
         // bitcast (inselt (bitcast X), Y, 0) --> or (and X, MaskC), (zext Y)

llvm/test/Transforms/InstCombine/bitcast-inselt-bitcast.ll

 ; LE-NEXT:    ret i32 [[R]]
 ;
   %v = bitcast i32 %x to <4 x i8>
   %i = insertelement <4 x i8> %v, i8 %y, i8 0
   %r = bitcast <4 x i8> %i to i32
   ret i32 %r
 }
 
+; i32 is a common type, so we can convert independently of the data layout.
+; Endian determines if a shift is needed (and so the transform is avoided).
+; half type can not be used in zext instruction (and so the transform is avoided).
+
+define i32 @insert0_v2half(i32 %x, half %y) {
+; BE-LABEL: @insert0_v2half(
+; BE-NEXT:    [[V:%.*]] = bitcast i32 [[X:%.*]] to <2 x half>
+; BE-NEXT:    [[I:%.*]] = insertelement <2 x half> [[V]], half [[Y:%.*]], i8 0
+; BE-NEXT:    [[R:%.*]] = bitcast <2 x half> [[I]] to i32
+; BE-NEXT:    ret i32 [[R]]
+;
+; LE-LABEL: @insert0_v2half(
+; LE-NEXT:    [[V:%.*]] = bitcast i32 [[X:%.*]] to <2 x half>
+; LE-NEXT:    [[I:%.*]] = insertelement <2 x half> [[V]], half [[Y:%.*]], i8 0
+; LE-NEXT:    [[R:%.*]] = bitcast <2 x half> [[I]] to i32
+; LE-NEXT:    ret i32 [[R]]
+;
+  %v = bitcast i32 %x to <2 x half>
+  %i = insertelement <2 x half> %v, half %y, i8 0
+  %r = bitcast <2 x half> %i to i32
+  ret i32 %r
+}
+
 ; i64 is a legal type, so we can convert based on the data layout.
 ; Endian determines if a shift is needed (and so the transform is avoided).
 
 define i64 @insert0_v4i16(i64 %x, i16 %y) {
 ; BE-LABEL: @insert0_v4i16(
 ; BE-NEXT:    [[V:%.*]] = bitcast i64 [[X:%.*]] to <4 x i16>
 ; BE-NEXT:    [[I:%.*]] = insertelement <4 x i16> [[V]], i16 [[Y:%.*]], i8 0
 ; BE-NEXT:    [[R:%.*]] = bitcast <4 x i16> [[I]] to i64