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[InstCombine] Allow fake vector insert folding to bit-logic only if the insert element is integer type
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Authored by Srividya-Karumuri on Nov 29 2021, 12:19 PM.

Details

Summary

The below commit is causing assertion when insert element type is not integer
type such as half. This is because the transformation is creating zext before
doing bitwise OR, and the zext is supported only for integer types
https://github.com/llvm/llvm-project/commit/80ab06c599a0f5a90951c36a57b2a9b492b19d61

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Event Timeline

Srividya-Karumuri requested review of this revision.Nov 29 2021, 12:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 29 2021, 12:19 PM
spatel accepted this revision.Nov 29 2021, 12:36 PM

LGTM - thanks for the fix!

This revision is now accepted and ready to land.Nov 29 2021, 12:36 PM