[clang] Add missing CPUID feature bit masks

[adamdb5]

Summary

Whilst working on a project which uses the x86 CPUID instruction, I noticed the header provided by clang (cpuid.h), is missing some bit masks for the feature registers.

I've implemented the missing masks, and also noticed that the previous mask
for PKU was shifted one bit too far to the right. It was 0b100, when it
should have been 0b1000.

Sources:
https://www.scss.tcd.ie/~jones/CS4021/processor-identification-cpuid-instruction-note.pdf
https://www.felixcloutier.com/x86/cpuid

This is my first commit, so please let me know if this is worth considering,
and any feedback is appreciated.

[adamdb5]

ran clang-format

[adamdb5]

[clang] Add missing CPUID feature bit masks

[craig.topper]

clang/lib/Headers/cpuid.h

101

Please don't change the formatting despite for the constants despite what the lint check says. Having then in columns is more readable.

[adamdb5]

undo clang-format

[pengfei]

In D114318#3144721, @adamdb5 wrote:

ran clang-format

I think we'd better to keep the existing format. It's in good readability.

clang/lib/Headers/cpuid.h

116

Where's this from. The latest SDM doesn't define this bit. I didn't find it in your link either.

147

Is there any other source using the same name? The same below.

152

SDM calls it "FDP_EXCPTN_ONLY". Don't know where's "EXCPTN" from.

173

This is reserved in latest SDM.

214

This is reserved in latest SDM.

222

Why not "AVX512VP2INT"?

[adamdb5]

Corrected issues.

Thanks for the feedback, please see the following comments:

bit_HYPERVISOR: This seems to be standardized. See the following links:

• https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery
• https://kb.vmware.com/s/article/1009458

Let me know if you think this shouldn't be added.

bit_IA64: I'm not entirely sure where I found this. I think it might have been wikipedia or something. I have removed it.

bit_TSCADJUST: Changed to match Intel SDM (IA32_TSC_ADJUST).

bit_FPUEXCEPT: Changed to match Intel SDM (FDP_EXCPTN_ONLY).

bit_LA57: Appears to be defined in June 2021 Intel SDM at Vol. 2A 3-219 (PDF page 794).

bit_AVX512VPCINT: Typo, changed to match Intel SDM (AVX512VP2INT).

[pengfei]

bit_HYPERVISOR: This seems to be standardized. See the following links:

I'm not sure what are these bits defined according to. From PV of HW, I think this shouldn't be added. This bit is set by hypervisor rather than CPU like others. And I found this bit is still 0 in my VM.

bit_IA57: Appears to be defined in June 2021 Intel SDM at Vol. 2A 3-219 (PDF page 794).

Oh, I missed that. Thanks.

GCC has the same (but fewer) definitions, https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h
[e-mail] to have a look.

clang/lib/Headers/cpuid.h

159

DEPR_FPU_CSDS ?

[adamdb5]

Renamed bit_DEPRFPUCSDS to bit_DEPR_FPU_CSDS

clang/lib/Headers/cpuid.h

 #define bit_MONITOR     0x00000008
 #define bit_DSCPL       0x00000010
 #define bit_VMX         0x00000020
 #define bit_SMX         0x00000040
 #define bit_EIST        0x00000080
 #define bit_TM2         0x00000100
 #define bit_SSSE3       0x00000200
 #define bit_CNXTID      0x00000400
+#define bit_SDBG        0x00000800
 #define bit_FMA         0x00001000
 #define bit_CMPXCHG16B  0x00002000
 #define bit_xTPR        0x00004000
 #define bit_PDCM        0x00008000
 #define bit_PCID        0x00020000
 #define bit_DCA         0x00040000
 #define bit_SSE41       0x00080000
 #define bit_SSE4_1      bit_SSE41       /* for gcc compat */
 #define bit_SSE42       0x00100000
 #define bit_SSE4_2      bit_SSE42       /* for gcc compat */
 #define bit_x2APIC      0x00200000
 #define bit_MOVBE       0x00400000
 #define bit_POPCNT      0x00800000
 #define bit_TSCDeadline 0x01000000
 #define bit_AESNI       0x02000000
 #define bit_AES         bit_AESNI       /* for gcc compat */
 #define bit_XSAVE       0x04000000
 #define bit_OSXSAVE     0x08000000
 #define bit_AVX         0x10000000
 #define bit_F16C        0x20000000
 #define bit_RDRND       0x40000000
+#define bit_HYPERVISOR  0x80000000
 
 /* Features in %edx for leaf 1 */
 #define bit_FPU         0x00000001
 #define bit_VME         0x00000002
 #define bit_DE          0x00000004
 #define bit_PSE         0x00000008
 #define bit_TSC         0x00000010
 #define bit_MSR         0x00000020
 #define bit_PAE         0x00000040
 #define bit_MCE         0x00000080
 #define bit_CX8         0x00000100
 #define bit_CMPXCHG8B   bit_CX8         /* for gcc compat */
 #define bit_APIC        0x00000200
 #define bit_SEP         0x00000800

 #define bit_SSE         0x02000000
 #define bit_SSE2        0x04000000
 #define bit_SS          0x08000000
 #define bit_HTT         0x10000000
 #define bit_TM          0x20000000
 #define bit_PBE         0x80000000
 
 /* Features in %ebx for leaf 7 sub-leaf 0 */
-#define bit_FSGSBASE    0x00000001
-#define bit_SGX         0x00000004
-#define bit_BMI         0x00000008
-#define bit_HLE         0x00000010
-#define bit_AVX2        0x00000020
-#define bit_SMEP        0x00000080
-#define bit_BMI2        0x00000100
-#define bit_ENH_MOVSB   0x00000200
-#define bit_INVPCID     0x00000400
-#define bit_RTM         0x00000800
-#define bit_MPX         0x00004000
-#define bit_AVX512F     0x00010000
-#define bit_AVX512DQ    0x00020000
-#define bit_RDSEED      0x00040000
-#define bit_ADX         0x00080000
-#define bit_AVX512IFMA  0x00200000
-#define bit_CLFLUSHOPT  0x00800000
-#define bit_CLWB        0x01000000
-#define bit_AVX512PF    0x04000000
-#define bit_AVX512ER    0x08000000
-#define bit_AVX512CD    0x10000000
-#define bit_SHA         0x20000000
-#define bit_AVX512BW    0x40000000
-#define bit_AVX512VL    0x80000000
+#define bit_FSGSBASE        0x00000001
+#define bit_IA32_TSC_ADJUST 0x00000002
+#define bit_SGX             0x00000004
+#define bit_BMI             0x00000008
+#define bit_HLE             0x00000010
+#define bit_AVX2            0x00000020
+#define bit_FDP_EXCPTN_ONLY 0x00000040
+#define bit_SMEP            0x00000080
+#define bit_BMI2            0x00000100
+#define bit_ENH_MOVSB       0x00000200
+#define bit_INVPCID         0x00000400
+#define bit_RTM             0x00000800
+#define bit_RDTM            0x00001000
+#define bit_DEPR_FPU_CSDS   0x00002000
+#define bit_MPX             0x00004000
+#define bit_RDTA            0x00008000
+#define bit_AVX512F         0x00010000
+#define bit_AVX512DQ        0x00020000
+#define bit_RDSEED          0x00040000
+#define bit_ADX             0x00080000
+#define bit_AVX512IFMA      0x00200000
+#define bit_CLFLUSHOPT      0x00800000
+#define bit_CLWB            0x01000000
+#define bit_IPT             0x02000000
+#define bit_AVX512PF        0x04000000
+#define bit_AVX512ER        0x08000000
+#define bit_AVX512CD        0x10000000
+#define bit_SHA             0x20000000
+#define bit_AVX512BW        0x40000000
+#define bit_AVX512VL        0x80000000
 
 /* Features in %ecx for leaf 7 sub-leaf 0 */
 #define bit_PREFTCHWT1       0x00000001
 #define bit_AVX512VBMI       0x00000002
-#define bit_PKU              0x00000004
+#define bit_UMIP             0x00000004
+#define bit_PKU              0x00000008
 #define bit_OSPKE            0x00000010
 #define bit_WAITPKG          0x00000020
 #define bit_AVX512VBMI2      0x00000040
 #define bit_SHSTK            0x00000080
 #define bit_GFNI             0x00000100
 #define bit_VAES             0x00000200
 #define bit_VPCLMULQDQ       0x00000400
 #define bit_AVX512VNNI       0x00000800
 #define bit_AVX512BITALG     0x00001000
+#define bit_TME_EN           0x00002000
 #define bit_AVX512VPOPCNTDQ  0x00004000
+#define bit_LA57             0x00010000
 #define bit_RDPID            0x00400000
+#define bit_KL               0x00800000
 #define bit_CLDEMOTE         0x02000000
 #define bit_MOVDIRI          0x08000000
 #define bit_MOVDIR64B        0x10000000
 #define bit_ENQCMD           0x20000000
+#define bit_SGX_LC           0x40000000
+#define bit_PKS              0x80000000
 
 /* Features in %edx for leaf 7 sub-leaf 0 */
 #define bit_AVX5124VNNIW  0x00000004
 #define bit_AVX5124FMAPS  0x00000008
+#define bit_FSRM          0x00000010
 #define bit_UINTR         0x00000020
+#define bit_AVX512VP2INT  0x00000100
+#define bit_MD_CLEAR      0x00000400
 #define bit_SERIALIZE     0x00004000
+#define bit_HYBRID        0x00008000
 #define bit_TSXLDTRK      0x00010000
 #define bit_PCONFIG       0x00040000
 #define bit_IBT           0x00100000
 #define bit_AMXBF16       0x00400000
 #define bit_AVX512FP16    0x00800000
 #define bit_AMXTILE       0x01000000
 #define bit_AMXINT8       0x02000000
+#define bit_IBRS_IBPB     0x04000000
+#define bit_STIBP         0x08000000
+#define bit_L1DFLUSH      0x10000000
+#define bit_IA32_ARCH_CAP 0x20000000
+#define bit_IA32_CORE_CAP 0x40000000
+#define bit_SSBD          0x80000000
 
 /* Features in %eax for leaf 7 sub-leaf 1 */
 #define bit_AVXVNNI       0x00000008
 #define bit_AVX512BF16    0x00000020
 #define bit_HRESET        0x00400000
 
 /* Features in %eax for leaf 13 sub-leaf 1 */
 #define bit_XSAVEOPT    0x00000001