[AMDGPU] Remove a no-op check in the gfx90a hazard recognizer

[rampitec]

Summary

Also rename helper function accordingly.

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

for (const MachineOperand &Use : MI->explicit_uses()) {
     const int MaxWaitStates = 19;
 
     if (!Use.isReg())
       continue;
     unsigned Reg = Use.getReg();
     bool FullReg;
     const MachineInstr *MI1;
 
-    auto IsOverlappedDGEMMorXDLFn = [Reg, &IsMFMAFn, &FullReg, &MI1,
-                                     this](const MachineInstr &MI) {
+    auto IsOverlappedMFMAFn = [Reg, &IsMFMAFn, &FullReg, &MI1,
       if (!IsMFMAFn(MI))
         return false;
-      if (!isDGEMM(MI.getOpcode()) && !isXDL(ST, MI))
-        return false;
       Register DstReg = MI.getOperand(0).getReg();
       FullReg = (DstReg == Reg);
       MI1 = &MI;
       return TRI.regsOverlap(DstReg, Reg);
     };
 
     WaitStatesNeededForUse = LegacyVALUNotDotWritesVGPRWaitStates -
       getWaitStatesSinceDef(Reg, IsLegacyVALUNotDotFn, MaxWaitStates);
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
 
-    int NumWaitStates = getWaitStatesSinceDef(Reg, IsOverlappedDGEMMorXDLFn,
-                                              MaxWaitStates);
+    int NumWaitStates =
+        getWaitStatesSinceDef(Reg, IsOverlappedMFMAFn, MaxWaitStates);
     if (NumWaitStates == std::numeric_limits<int>::max())
       continue;
 
     int OpNo = MI->getOperandNo(&Use);
     unsigned Opc1 = MI1->getOpcode();
     int NeedWaitStates = 0;
     if (OpNo == SrcCIdx) {
       if (!isDGEMM(Opc) && isDGEMM(Opc1)) {
int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
   bool IsMemOrExport = SIInstrInfo::isVMEM(*MI) ||
                        SIInstrInfo::isFLAT(*MI) ||
                        SIInstrInfo::isDS(*MI) ||
                        SIInstrInfo::isEXP(*MI);
   bool IsVALU = SIInstrInfo::isVALU(*MI);
 
   const MachineInstr *MFMA = nullptr;
   unsigned Reg;
-  auto IsDGEMMorXDLWriteFn = [&Reg, &IsMFMAFn, &MFMA,
-                              this](const MachineInstr &MI) {
+  auto IsMFMAWriteFn = [&Reg, &IsMFMAFn, &MFMA, this](const MachineInstr &MI) {
     if (!IsMFMAFn(MI) || !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg))
       return false;
-    if (!isDGEMM(MI.getOpcode()) && !isXDL(ST, MI))
-      return false;
     MFMA = &MI;
     return true;
   };
 
   const MachineInstr *DOT = nullptr;
   auto IsDotWriteFn = [&Reg, &DOT, this](const MachineInstr &MI) {
     if (!SIInstrInfo::isDOT(MI) ||
         !TRI.regsOverlap(MI.getOperand(0).getReg(), Reg))
for (const MachineOperand &Use : MI->explicit_uses()) {
           NeedWaitStates = DotWriteDifferentVALURead;
         }
 
         int WaitStatesNeededForUse = NeedWaitStates - WaitStatesSinceDef;
         WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
       }
 
       MFMA = nullptr;
-      WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDGEMMorXDLWriteFn,
-                                                 MaxWaitStates);
+      WaitStatesSinceDef =
+          getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates);
       if (!MFMA)
         continue;
 
       unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA);
       int NeedWaitStates = MaxWaitStates;
       switch (HazardDefLatency) {
       case 2:
         NeedWaitStates = SMFMA4x4WriteVgprVALUMemExpReadWaitStates;
for (const MachineOperand &Def : MI->defs()) {
     DOT = nullptr;
     int WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDotWriteFn,
                                                    MaxWaitStates);
     if (DOT && DOT->getOpcode() != MI->getOpcode())
       WaitStatesNeeded = std::max(WaitStatesNeeded, DotWriteDifferentVALUWrite -
                                                     WaitStatesSinceDef);
 
     MFMA = nullptr;
-    WaitStatesSinceDef = getWaitStatesSinceDef(Reg, IsDGEMMorXDLWriteFn,
-                                               MaxWaitStates);
+    WaitStatesSinceDef =
+        getWaitStatesSinceDef(Reg, IsMFMAWriteFn, MaxWaitStates);
     if (MFMA) {
       int NeedWaitStates = MaxWaitStates;
       switch (TSchedModel.computeInstrLatency(MFMA)) {
       case 2:
         NeedWaitStates = SMFMA4x4WriteVgprVALUWawWaitStates;
         break;
       case 4:
         assert(isDGEMM(MFMA->getOpcode()));