[Loads] Handle addrspacecast constant expressions when determining dereferenceability

[aeubanks]

rebase

[nikic]

LG

[tra]

llvm/lib/Analysis/Loads.cpp

150

Do we need/want to handle Instr variant as well? Or does AddrSpaceCastOperator handle both ASC variants?

[aeubanks]

llvm/lib/Analysis/Loads.cpp

150

yes AddrSpaceCastOperator handles both

llvm/lib/Analysis/Loads.cpp

static bool isDereferenceableAndAlignedPointer(
   }
 
   // For gc.relocate, look through relocations
   if (const GCRelocateInst *RelocateInst = dyn_cast<GCRelocateInst>(V))
     return isDereferenceableAndAlignedPointer(RelocateInst->getDerivedPtr(),
                                               Alignment, Size, DL, CtxI, DT,
                                               TLI, Visited, MaxDepth);
 
-  if (const AddrSpaceCastInst *ASC = dyn_cast<AddrSpaceCastInst>(V))
+  if (const AddrSpaceCastOperator *ASC = dyn_cast<AddrSpaceCastOperator>(V))
     return isDereferenceableAndAlignedPointer(ASC->getOperand(0), Alignment,
                                               Size, DL, CtxI, DT, TLI,
                                               Visited, MaxDepth);
 
   if (const auto *Call = dyn_cast<CallBase>(V)) {
     if (auto *RP = getArgumentAliasingToReturnedPointer(Call, true))
       return isDereferenceableAndAlignedPointer(RP, Alignment, Size, DL, CtxI,
                                                 DT, TLI, Visited, MaxDepth);

llvm/test/Transforms/SROA/addrspacecast.ll

entry:
   %val = load i64, i64* %gep.bitcast
   ret i64 %val
 }
 
 ; Don't change the address space of a volatile operation
 define i64 @alloca_addrspacecast_bitcast_volatile_store(i64 %X) {
 ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_store(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8], align 1
 ; CHECK-NEXT:    [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)*
 ; CHECK-NEXT:    [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)*
-; CHECK-NEXT:    store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]]
-; CHECK-NEXT:    [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]]
+; CHECK-NEXT:    store volatile i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4
+; CHECK-NEXT:    [[Z:%.*]] = load i64, i64 addrspace(1)* [[B]], align 4
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
 entry:
   %A = alloca [8 x i8]
   %A.cast = addrspacecast [8 x i8]* %A to [8 x i8] addrspace(1)*
   %B = bitcast [8 x i8] addrspace(1)* %A.cast to i64 addrspace(1)*
   store volatile i64 %X, i64 addrspace(1)* %B
   %Z = load i64, i64 addrspace(1)* %B
   ret i64 %Z
 }
 
 ; Don't change the address space of a volatile operation
 define i64 @alloca_addrspacecast_bitcast_volatile_load(i64 %X) {
 ; CHECK-LABEL: @alloca_addrspacecast_bitcast_volatile_load(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [8 x i8], align 1
 ; CHECK-NEXT:    [[A_CAST:%.*]] = addrspacecast [8 x i8]* [[A]] to [8 x i8] addrspace(1)*
 ; CHECK-NEXT:    [[B:%.*]] = bitcast [8 x i8] addrspace(1)* [[A_CAST]] to i64 addrspace(1)*
-; CHECK-NEXT:    store i64 [[X:%.*]], i64 addrspace(1)* [[B]]
-; CHECK-NEXT:    [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]]
+; CHECK-NEXT:    store i64 [[X:%.*]], i64 addrspace(1)* [[B]], align 4
+; CHECK-NEXT:    [[Z:%.*]] = load volatile i64, i64 addrspace(1)* [[B]], align 4
 ; CHECK-NEXT:    ret i64 [[Z]]
 ;
 entry:
   %A = alloca [8 x i8]
   %A.cast = addrspacecast [8 x i8]* %A to [8 x i8] addrspace(1)*
   %B = bitcast [8 x i8] addrspace(1)* %A.cast to i64 addrspace(1)*
   store i64 %X, i64 addrspace(1)* %B
   %Z = load volatile i64, i64 addrspace(1)* %B
   ret i64 %Z
 }
 
 declare void @llvm.memset.p1i8.i32(i8 addrspace(1)* nocapture, i8, i32, i1) nounwind
 
 ; Don't change the address space of a volatile operation
 define i32 @volatile_memset() {
 ; CHECK-LABEL: @volatile_memset(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8], align 1
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0
 ; CHECK-NEXT:    [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)*
 ; CHECK-NEXT:    call void @llvm.memset.p1i8.i32(i8 addrspace(1)* [[ASC]], i8 42, i32 4, i1 true)
 ; CHECK-NEXT:    [[IPTR:%.*]] = bitcast i8* [[PTR]] to i32*
-; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[IPTR]]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[IPTR]], align 4
 ; CHECK-NEXT:    ret i32 [[VAL]]
 ;
 entry:
   %a = alloca [4 x i8]
   %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   %asc = addrspacecast i8* %ptr to i8 addrspace(1)*
   call void @llvm.memset.p1i8.i32(i8 addrspace(1)* %asc, i8 42, i32 4, i1 true)
   %iptr = bitcast i8* %ptr to i32*
   %val = load i32, i32* %iptr
   ret i32 %val
 }
 
 ; Don't change the address space of a volatile operation
 define void @volatile_memcpy(i8* %src, i8* %dst) {
 ; CHECK-LABEL: @volatile_memcpy(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8]
+; CHECK-NEXT:    [[A:%.*]] = alloca [4 x i8], align 1
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr [4 x i8], [4 x i8]* [[A]], i32 0, i32 0
 ; CHECK-NEXT:    [[ASC:%.*]] = addrspacecast i8* [[PTR]] to i8 addrspace(1)*
-; CHECK-NEXT:    call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa !0
-; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa !3
+; CHECK-NEXT:    call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* [[ASC]], i8* [[SRC:%.*]], i32 4, i1 true), !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT:    call void @llvm.memcpy.p0i8.p1i8.i32(i8* [[DST:%.*]], i8 addrspace(1)* [[ASC]], i32 4, i1 true), !tbaa [[TBAA3:![0-9]+]]
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %a = alloca [4 x i8]
   %ptr = getelementptr [4 x i8], [4 x i8]* %a, i32 0, i32 0
   %asc = addrspacecast i8* %ptr to i8 addrspace(1)*
   call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %asc, i8* %src, i32 4, i1 true), !tbaa !0
   call void @llvm.memcpy.p0i8.p1i8.i32(i8* %dst, i8 addrspace(1)* %asc, i32 4, i1 true), !tbaa !3
;
   %p.0.c = select i1 undef, i64* %c, i64* %c
   %asc = addrspacecast i64* %p.0.c to i64 addrspace(1)*
 
   %cond.in = select i1 undef, i64 addrspace(1)* %asc, i64 addrspace(1)* @gv
   %cond = load i64, i64 addrspace(1)* %cond.in, align 8
   ret void
 }
 
+define void @select_addrspacecast_gv_constexpr(i1 %a, i1 %b) {
+; CHECK-LABEL: @select_addrspacecast_gv_constexpr(
+; CHECK-NEXT:    [[COND_SROA_SPECULATE_LOAD_FALSE:%.*]] = load i64, i64 addrspace(2)* addrspacecast (i64 addrspace(1)* @gv to i64 addrspace(2)*), align 8
+; CHECK-NEXT:    [[COND_SROA_SPECULATED:%.*]] = select i1 undef, i64 undef, i64 [[COND_SROA_SPECULATE_LOAD_FALSE]]
+; CHECK-NEXT:    ret void
+;
+  %c = alloca i64, align 8
+  %p.0.c = select i1 undef, i64* %c, i64* %c
+  %asc = addrspacecast i64* %p.0.c to i64 addrspace(2)*
+
+  %cond.in = select i1 undef, i64 addrspace(2)* %asc, i64 addrspace(2)* addrspacecast (i64 addrspace(1)* @gv to i64 addrspace(2)*)
+  %cond = load i64, i64 addrspace(2)* %cond.in, align 8
+  ret void
+}
+
 define i8 @select_addrspacecast_i8() {
 ; CHECK-LABEL: @select_addrspacecast_i8(
 ; CHECK-NEXT:    [[RET_SROA_SPECULATED:%.*]] = select i1 undef, i8 undef, i8 undef
 ; CHECK-NEXT:    ret i8 [[RET_SROA_SPECULATED]]
 ;
   %a = alloca i8
   %b = alloca i8