[X86][Costmodel] Load/store i32/f32 Stride=6 VF=8 interleaving costs

[lebedev.ri]

Summary

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/jK85GWKaK - for intels Block RThroughput: =31.0; for ryzens, Block RThroughput: <=17.0
So could pick cost of 31.

For store we have:
https://godbolt.org/z/hPWWhEEf9 - for intels Block RThroughput: =33.0; for ryzens, Block RThroughput: <=13.8
So we could pick cost of 33.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

[RKSimon]

LGTM

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
   // Factor (stride) and VectorType=VFxiN.
   // The Cost accounts only for the shuffle sequence;
   // The cost of the loads/stores is accounted for separately.
   //
   static const CostTblEntry AVX2InterleavedLoadTbl[] = {
       {2, MVT::v2i8, 2},  // (load 4i8 and) deinterleave into 2 x 2i8
       {2, MVT::v4i8, 2},  // (load 8i8 and) deinterleave into 2 x 4i8
       {2, MVT::v8i8, 2},  // (load 16i8 and) deinterleave into 2 x 8i8
       {2, MVT::v16i8, 4},  // (load 32i8 and) deinterleave into 2 x 16i8
       {2, MVT::v32i8, 6},  // (load 64i8 and) deinterleave into 2 x 32i8
 
       {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16
       {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16
       {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16
       {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16
       {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16
 
       {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32
       {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32
       {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32
       {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32
       {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32
 
       {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64
       {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64
       {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64
       {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64
 
       {3, MVT::v2i8, 3},  // (load 6i8 and) deinterleave into 3 x 2i8
       {3, MVT::v4i8, 3},   // (load 12i8 and) deinterleave into 3 x 4i8
       {3, MVT::v8i8, 6},   // (load 24i8 and) deinterleave into 3 x 8i8
       {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8
       {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8
 
       {3, MVT::v2i16, 5},  // (load 6i16 and) deinterleave into 3 x 2i16
       {3, MVT::v4i16, 7},  // (load 12i16 and) deinterleave into 3 x 4i16
       {3, MVT::v8i16, 9},  // (load 24i16 and) deinterleave into 3 x 8i16
       {3, MVT::v16i16, 28},  // (load 48i16 and) deinterleave into 3 x 16i16
       {3, MVT::v32i16, 56},  // (load 96i16 and) deinterleave into 3 x 32i16
 
       {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32
       {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32
       {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32
       {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32
 
       {3, MVT::v2i64, 1},  // (load 6i64 and) deinterleave into 3 x 2i64
       {3, MVT::v4i64, 5},  // (load 12i64 and) deinterleave into 3 x 4i64
       {3, MVT::v8i64, 10},  // (load 24i64 and) deinterleave into 3 x 8i64
       {3, MVT::v16i64, 20},  // (load 48i64 and) deinterleave into 3 x 16i64
 
       {4, MVT::v2i8, 4},  // (load 8i8 and) deinterleave into 4 x 2i8
       {4, MVT::v4i8, 4},   // (load 16i8 and) deinterleave into 4 x 4i8
       {4, MVT::v8i8, 12},  // (load 32i8 and) deinterleave into 4 x 8i8
       {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8
       {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8
 
       {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16
       {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16
       {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16
       {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16
       {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16
 
       {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8
       {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8
       {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8
       {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8
       {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8
 
       {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16
       {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16
       {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16
       {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16
 
       {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32
       {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32
+      {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32
 
       {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
   };
 
   static const CostTblEntry AVX2InterleavedStoreTbl[] = {
       {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store)
       {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store)
       {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store)
       {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store)
       {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store)
 
       {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store)
       {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store)
       {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store)
       {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store)
       {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store)
 
       {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store)
       {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store)
       {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store)
       {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store)
       {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store)
 
       {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store)
       {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store)
       {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store)
       {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store)
 
       {3, MVT::v2i8, 4},   // interleave 3 x 2i8 into 6i8 (and store)
       {3, MVT::v4i8, 4},   // interleave 3 x 4i8 into 12i8 (and store)
       {3, MVT::v8i8, 6},  // interleave 3 x 8i8 into 24i8 (and store)
       {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store)
       {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store)
 
       {3, MVT::v2i16, 4},   // interleave 3 x 2i16 into 6i16 (and store)
       {3, MVT::v4i16, 6},   // interleave 3 x 4i16 into 12i16 (and store)
       {3, MVT::v8i16, 12},   // interleave 3 x 8i16 into 24i16 (and store)
       {3, MVT::v16i16, 27},   // interleave 3 x 16i16 into 48i16 (and store)
       {3, MVT::v32i16, 54},   // interleave 3 x 32i16 into 96i16 (and store)
 
       {3, MVT::v2i32, 4},   // interleave 3 x 2i32 into 6i32 (and store)
       {3, MVT::v4i32, 5},   // interleave 3 x 4i32 into 12i32 (and store)
       {3, MVT::v8i32, 11},   // interleave 3 x 8i32 into 24i32 (and store)
       {3, MVT::v16i32, 22},   // interleave 3 x 16i32 into 48i32 (and store)
 
       {3, MVT::v2i64, 4},   // interleave 3 x 2i64 into 6i64 (and store)
       {3, MVT::v4i64, 6},   // interleave 3 x 4i64 into 12i64 (and store)
       {3, MVT::v8i64, 12},   // interleave 3 x 8i64 into 24i64 (and store)
       {3, MVT::v16i64, 24},   // interleave 3 x 16i64 into 48i64 (and store)
 
       {4, MVT::v2i8, 4},  // interleave 4 x 2i8 into 8i8 (and store)
       {4, MVT::v4i8, 4},   // interleave 4 x 4i8 into 16i8 (and store)
       {4, MVT::v8i8, 4},  // interleave 4 x 8i8 into 32i8 (and store)
       {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store)
       {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store)
 
       {4, MVT::v2i16, 2},  // interleave 4 x 2i16 into 8i16 (and store)
       {4, MVT::v4i16, 6},  // interleave 4 x 4i16 into 16i16 (and store)
       {4, MVT::v8i16, 10},  // interleave 4 x 8i16 into 32i16 (and store)
       {4, MVT::v16i16, 32},  // interleave 4 x 16i16 into 64i16 (and store)
       {4, MVT::v32i16, 64},  // interleave 4 x 32i16 into 128i16 (and store)
 
       {6, MVT::v2i8, 7},  // interleave 6 x 2i8 into 12i8 (and store)
       {6, MVT::v4i8, 9},  // interleave 6 x 4i8 into 24i8 (and store)
       {6, MVT::v8i8, 16},  // interleave 6 x 8i8 into 48i8 (and store)
       {6, MVT::v16i8, 27},  // interleave 6 x 16i8 into 96i8 (and store)
       {6, MVT::v32i8, 90},  // interleave 6 x 32i8 into 192i8 (and store)
 
       {6, MVT::v2i16, 10},  // interleave 6 x 2i16 into 12i16 (and store)
       {6, MVT::v4i16, 15},  // interleave 6 x 4i16 into 24i16 (and store)
       {6, MVT::v8i16, 21},  // interleave 6 x 8i16 into 48i16 (and store)
       {6, MVT::v16i16, 58},  // interleave 6 x 16i16 into 96i16 (and store)
 
       {6, MVT::v2i32, 9},  // interleave 6 x 2i32 into 12i32 (and store)
       {6, MVT::v4i32, 12},  // interleave 6 x 4i32 into 24i32 (and store)
+      {6, MVT::v8i32, 33},  // interleave 6 x 8i32 into 48i32 (and store)
   };
 
   if (Opcode == Instruction::Load) {
     if (const auto *Entry =
             CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT()))
       return MemOpCosts + Entry->Cost;
   } else {
     assert(Opcode == Instruction::Store &&

llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll

 ; AVX1: LV: Found an estimated cost of 21 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 51 for VF 4 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 114 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 228 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction:   %v0 = load float, float* %in0, align 4
-; AVX2: LV: Found an estimated cost of 114 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
+; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 11 for VF 4 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 21 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 51 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 210 for VF 32 For instruction:   %v0 = load float, float* %in0, align 4

llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll

 ; AVX1: LV: Found an estimated cost of 30 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 63 for VF 4 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 138 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX1: LV: Found an estimated cost of 276 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction:   %v0 = load i32, i32* %in0, align 4
-; AVX2: LV: Found an estimated cost of 138 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
+; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 11 for VF 4 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 21 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 51 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 210 for VF 32 For instruction:   %v0 = load i32, i32* %in0, align 4

llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll

 ; AVX1: LV: Found an estimated cost of 20 for VF 2 For instruction:   store float %v5, float* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 45 for VF 4 For instruction:   store float %v5, float* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 114 for VF 8 For instruction:   store float %v5, float* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 228 for VF 16 For instruction:   store float %v5, float* %out5, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store float %v5, float* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store float %v5, float* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction:   store float %v5, float* %out5, align 4
-; AVX2: LV: Found an estimated cost of 114 for VF 8 For instruction:   store float %v5, float* %out5, align 4
+; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction:   store float %v5, float* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction:   store float %v5, float* %out5, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 17 for VF 4 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 25 for VF 8 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 51 for VF 16 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 102 for VF 32 For instruction:   store float %v5, float* %out5, align 4

llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll

 ; AVX1: LV: Found an estimated cost of 29 for VF 2 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 57 for VF 4 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 138 for VF 8 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX1: LV: Found an estimated cost of 276 for VF 16 For instruction:   store i32 %v5, i32* %out5, align 4
 ;
 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction:   store i32 %v5, i32* %out5, align 4
-; AVX2: LV: Found an estimated cost of 138 for VF 8 For instruction:   store i32 %v5, i32* %out5, align 4
+; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction:   store i32 %v5, i32* %out5, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 17 for VF 4 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 25 for VF 8 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 51 for VF 16 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 102 for VF 32 For instruction:   store i32 %v5, i32* %out5, align 4