[X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A).

[LiuChen3]

Summary

This bug was introduced by D109953. The operand order of generated FMA
is wrong.

[pengfei]

My fault. I missed to change here. Thanks Chen! LGTM.

[FreddyYe]

LGTM.

[LiuChen3]

Fix check-all fail.

[LiuChen3]

Can you take a review again and +1 if no problem? I missed changing some testcases. Thanks.

[FreddyYe]

LGTM.

[LiuChen3]

Thanks for you review.

llvm/lib/Target/X86/X86ISelLowering.cpp

else
     return SDValue();
 
   MVT CVT = MVT::getVectorVT(MVT::f32, VT.getVectorNumElements() / 2);
   FAddOp1 = DAG.getBitcast(CVT, FAddOp1);
   unsigned NewOp = IsConj ? X86ISD::VFCMADDC : X86ISD::VFMADDC;
   // FIXME: How do we handle when fast math flags of FADD are different from
   // CFMUL's?
   SDValue CFmul =
-      DAG.getNode(NewOp, SDLoc(N), CVT, FAddOp1, MulOp0, MulOp1, N->getFlags());
+      DAG.getNode(NewOp, SDLoc(N), CVT, MulOp0, MulOp1, FAddOp1, N->getFlags());
   return DAG.getBitcast(VT, CFmul);
 }
 
 /// Do target-specific dag combines on floating-point adds/subs.
 static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG,
                                const X86Subtarget &Subtarget) {
   if (SDValue HOp = combineToHorizontalAddSub(N, DAG, Subtarget))
     return HOp;

llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=fast --enable-no-signed-zeros-fp-math -mattr=avx512fp16 | FileCheck %s --check-prefixes=CHECK,NO-SZ
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown --fp-contract=fast -mattr=avx512fp16 | FileCheck %s --check-prefixes=CHECK,HAS-SZ
 
 ; FADD(acc, FMA(a, b, +0.0)) can be combined to FMA(a, b, acc) if the nsz flag set.
 define dso_local <32 x half> @test1(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
 ; NO-SZ-LABEL: test1:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfcmaddcph %zmm1, %zmm0, %zmm2
-; NO-SZ-NEXT:    vmovaps %zmm2, %zmm0
+; NO-SZ-NEXT:    vfcmaddcph %zmm2, %zmm1, %zmm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test1:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfcmaddcph %zmm2, %zmm1, %zmm3
 ; HAS-SZ-NEXT:    vaddph %zmm0, %zmm3, %zmm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %a to <16 x float>
   %1 = bitcast <32 x half> %b to <16 x float>
   %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add.i = fadd <32 x half> %3, %acc
   ret <32 x half> %add.i
 }
 
 define dso_local <32 x half> @test2(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
 ; NO-SZ-LABEL: test2:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfmaddcph %zmm1, %zmm0, %zmm2
-; NO-SZ-NEXT:    vmovaps %zmm2, %zmm0
+; NO-SZ-NEXT:    vfmaddcph %zmm2, %zmm1, %zmm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test2:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfmaddcph %zmm2, %zmm1, %zmm3
 ; HAS-SZ-NEXT:    vaddph %zmm0, %zmm3, %zmm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %a to <16 x float>
   %1 = bitcast <32 x half> %b to <16 x float>
   %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add.i = fadd <32 x half> %3, %acc
   ret <32 x half> %add.i
 }
 
 define dso_local <16 x half> @test3(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
 ; NO-SZ-LABEL: test3:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfcmaddcph %ymm1, %ymm0, %ymm2
-; NO-SZ-NEXT:    vmovaps %ymm2, %ymm0
+; NO-SZ-NEXT:    vfcmaddcph %ymm2, %ymm1, %ymm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test3:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfcmaddcph %ymm2, %ymm1, %ymm3
 ; HAS-SZ-NEXT:    vaddph %ymm0, %ymm3, %ymm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %a to <8 x float>
   %1 = bitcast <16 x half> %b to <8 x float>
   %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
   %3 = bitcast <8 x float> %2 to <16 x half>
   %add.i = fadd <16 x half> %3, %acc
   ret <16 x half> %add.i
 }
 
 define dso_local <16 x half> @test4(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
 ; NO-SZ-LABEL: test4:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfmaddcph %ymm1, %ymm0, %ymm2
-; NO-SZ-NEXT:    vmovaps %ymm2, %ymm0
+; NO-SZ-NEXT:    vfmaddcph %ymm2, %ymm1, %ymm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test4:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfmaddcph %ymm2, %ymm1, %ymm3
 ; HAS-SZ-NEXT:    vaddph %ymm0, %ymm3, %ymm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %a to <8 x float>
   %1 = bitcast <16 x half> %b to <8 x float>
   %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
   %3 = bitcast <8 x float> %2 to <16 x half>
   %add.i = fadd <16 x half> %3, %acc
   ret <16 x half> %add.i
 }
 
 define dso_local <8 x half> @test5(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
 ; NO-SZ-LABEL: test5:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfcmaddcph %xmm1, %xmm0, %xmm2
-; NO-SZ-NEXT:    vmovaps %xmm2, %xmm0
+; NO-SZ-NEXT:    vfcmaddcph %xmm2, %xmm1, %xmm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test5:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfcmaddcph %xmm2, %xmm1, %xmm3
 ; HAS-SZ-NEXT:    vaddph %xmm0, %xmm3, %xmm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %a to <4 x float>
   %1 = bitcast <8 x half> %b to <4 x float>
   %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i = fadd <8 x half> %3, %acc
   ret <8 x half> %add.i
 }
 
 define dso_local <8 x half> @test6(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
 ; NO-SZ-LABEL: test6:
 ; NO-SZ:       # %bb.0: # %entry
-; NO-SZ-NEXT:    vfmaddcph %xmm1, %xmm0, %xmm2
-; NO-SZ-NEXT:    vmovaps %xmm2, %xmm0
+; NO-SZ-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm0
 ; NO-SZ-NEXT:    retq
 ;
 ; HAS-SZ-LABEL: test6:
 ; HAS-SZ:       # %bb.0: # %entry
 ; HAS-SZ-NEXT:    vxorps %xmm3, %xmm3, %xmm3
 ; HAS-SZ-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm3
 ; HAS-SZ-NEXT:    vaddph %xmm0, %xmm3, %xmm0
 ; HAS-SZ-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %a to <4 x float>
   %1 = bitcast <8 x half> %b to <4 x float>
   %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i = fadd <8 x half> %3, %acc
   ret <8 x half> %add.i
 }
 
 ; FADD(acc, FMA(a, b, -0.0)) can be combined to FMA(a, b, acc) no matter if the nsz flag set.
 define dso_local <32 x half> @test13(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
 ; CHECK-LABEL: test13:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %zmm1, %zmm0, %zmm2
-; CHECK-NEXT:    vmovaps %zmm2, %zmm0
+; CHECK-NEXT:    vfcmaddcph %zmm2, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %a to <16 x float>
   %1 = bitcast <32 x half> %b to <16 x float>
   %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add.i = fadd <32 x half> %3, %acc
   ret <32 x half> %add.i
 }
 
 define dso_local <32 x half> @test14(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
 ; CHECK-LABEL: test14:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %zmm1, %zmm0, %zmm2
-; CHECK-NEXT:    vmovaps %zmm2, %zmm0
+; CHECK-NEXT:    vfmaddcph %zmm2, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %a to <16 x float>
   %1 = bitcast <32 x half> %b to <16 x float>
   %2 = tail call <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add.i = fadd <32 x half> %3, %acc
   ret <32 x half> %add.i
 }
 
 define dso_local <16 x half> @test15(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
 ; CHECK-LABEL: test15:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %ymm1, %ymm0, %ymm2
-; CHECK-NEXT:    vmovaps %ymm2, %ymm0
+; CHECK-NEXT:    vfcmaddcph %ymm2, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %a to <8 x float>
   %1 = bitcast <16 x half> %b to <8 x float>
   %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
   %3 = bitcast <8 x float> %2 to <16 x half>
   %add.i = fadd <16 x half> %3, %acc
   ret <16 x half> %add.i
 }
 
 define dso_local <16 x half> @test16(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
 ; CHECK-LABEL: test16:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %ymm1, %ymm0, %ymm2
-; CHECK-NEXT:    vmovaps %ymm2, %ymm0
+; CHECK-NEXT:    vfmaddcph %ymm2, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %a to <8 x float>
   %1 = bitcast <16 x half> %b to <8 x float>
   %2 = tail call <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
   %3 = bitcast <8 x float> %2 to <16 x half>
   %add.i = fadd <16 x half> %3, %acc
   ret <16 x half> %add.i
 }
 
 define dso_local <8 x half> @test17(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test17:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %xmm1, %xmm0, %xmm2
-; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vfcmaddcph %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %a to <4 x float>
   %1 = bitcast <8 x half> %b to <4 x float>
   %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i = fadd <8 x half> %3, %acc
   ret <8 x half> %add.i
 }
 
 define dso_local <8 x half> @test18(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: test18:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %xmm1, %xmm0, %xmm2
-; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %a to <4 x float>
   %1 = bitcast <8 x half> %b to <4 x float>
   %2 = tail call <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i = fadd <8 x half> %3, %acc
   ret <8 x half> %add.i
 }
 
 declare <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
 declare <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
 declare <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
 declare <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
 declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)
 declare <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)

llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16 --fp-contract=fast --enable-unsafe-fp-math | FileCheck %s
 
 define dso_local <32 x half> @test1(<32 x half> %acc.coerce, <32 x half> %lhs.coerce, <32 x half> %rhs.coerce) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %zmm1, %zmm0, %zmm2
-; CHECK-NEXT:    vmovaps %zmm2, %zmm0
+; CHECK-NEXT:    vfmaddcph %zmm2, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %lhs.coerce to <16 x float>
   %1 = bitcast <32 x half> %rhs.coerce to <16 x float>
   %2 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add.i.i = fadd fast <32 x half> %3, %acc.coerce
   ret <32 x half> %add.i.i
 }
 
 define dso_local <16 x half> @test2(<16 x half> %acc.coerce, <16 x half> %lhs.coerce, <16 x half> %rhs.coerce) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %ymm1, %ymm0, %ymm2
-; CHECK-NEXT:    vmovaps %ymm2, %ymm0
+; CHECK-NEXT:    vfmaddcph %ymm2, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %lhs.coerce to <8 x float>
   %1 = bitcast <16 x half> %rhs.coerce to <8 x float>
   %2 = tail call fast <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
   %3 = bitcast <8 x float> %2 to <16 x half>
   %add.i.i = fadd fast <16 x half> %3, %acc.coerce
   ret <16 x half> %add.i.i
 }
 
 define dso_local <8 x half> @test3(<8 x half> %acc.coerce, <8 x half> %lhs.coerce, <8 x half> %rhs.coerce) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %xmm1, %xmm0, %xmm2
-; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce to <4 x float>
   %1 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %2 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i.i = fadd fast <8 x half> %3, %acc.coerce
   ret <8 x half> %add.i.i
 }
 
 
 define dso_local <8 x half> @test4(<8 x half> %acc.coerce, <8 x half> %lhs.coerce, <8 x half> %rhs.coerce) {
 ; CHECK-LABEL: test4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfmaddcph %xmm1, %xmm0, %xmm2
-; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce to <4 x float>
   %1 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %2 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
   %3 = bitcast <4 x float> %2 to <8 x half>
   %add.i.i = fadd fast <8 x half> %acc.coerce, %3
   ret <8 x half> %add.i.i
 }
 
 declare <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
 declare <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
 declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)

llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16 --fp-contract=fast --enable-unsafe-fp-math | FileCheck %s
 
 define dso_local <32 x half> @test1(<32 x half> %acc.coerce, <32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %zmm2, %zmm0, %zmm1
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
+; CHECK-NEXT:    vfcmaddcph %zmm1, %zmm2, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %lhs.coerce.conj to <16 x i32>
   %xor.i.i = xor <16 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
   %1 = bitcast <16 x i32> %xor.i.i to <16 x float>
   %2 = bitcast <32 x half> %rhs.coerce to <16 x float>
   %3 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %1, <16 x float> %2, <16 x float> zeroinitializer, i16 -1, i32 4) #2
   %4 = bitcast <16 x float> %3 to <32 x half>
   %add = fadd fast <32 x half> %4, %acc.coerce
   ret <32 x half> %add
 }
 
 define dso_local <32 x half> @test2(<32 x half> %acc.coerce, <32 x half> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %zmm2, %zmm0, %zmm1
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
+; CHECK-NEXT:    vfcmaddcph %zmm1, %zmm2, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <32 x half> %lhs.coerce.conj to <16 x i32>
   %xor.i.i = xor <16 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
   %1 = bitcast <16 x i32> %xor.i.i to <16 x float>
   %2 = bitcast <32 x half> %rhs.coerce to <16 x float>
   %3 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %2, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4) #2
   %4 = bitcast <16 x float> %3 to <32 x half>
   %add = fadd fast <32 x half> %4, %acc.coerce
   ret <32 x half> %add
 }
 
 define dso_local <16 x half> @test3(<16 x half> %acc.coerce, <16 x half> %lhs.coerce.conj, <16 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %ymm2, %ymm0, %ymm1
-; CHECK-NEXT:    vmovaps %ymm1, %ymm0
+; CHECK-NEXT:    vfcmaddcph %ymm1, %ymm2, %ymm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <16 x half> %lhs.coerce.conj to <8 x i32>
   %xor.i.i = xor <8 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
   %1 = bitcast <8 x i32> %xor.i.i to <8 x float>
   %2 = bitcast <16 x half> %rhs.coerce to <8 x float>
   %3 = tail call fast <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float> %1, <8 x float> %2, <8 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <8 x float> %3 to <16 x half>
   %add = fadd fast <16 x half> %4, %acc.coerce
   ret <16 x half> %add
 }
 
 define dso_local <8 x half> @test4(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test4:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %xmm2, %xmm0, %xmm1
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:    vfcmaddcph %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>
   %xor.i.i = xor <4 x i32> %0, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
   %1 = bitcast <4 x i32> %xor.i.i to <4 x float>
   %2 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <4 x float> %3 to <8 x half>
   %add = fadd fast <8 x half> %4, %acc.coerce
   ret <8 x half> %add
 }
 
 define dso_local <8 x half> @test5(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test5:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %xmm2, %xmm0, %xmm1
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:    vfcmaddcph %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>
   %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %0
   %1 = bitcast <4 x i32> %xor.i.i to <4 x float>
   %2 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <4 x float> %3 to <8 x half>
   %add = fadd fast <8 x half> %4, %acc.coerce
   ret <8 x half> %add
 }
 
 define dso_local <8 x half> @test6(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
-; CHECK-NEXT:    vfmaddcph %xmm1, %xmm0, %xmm2
-; CHECK-NEXT:    vmovaps %xmm2, %xmm0
+; CHECK-NEXT:    vfmaddcph %xmm2, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>
   %xor.i.i = xor <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %0
   %1 = bitcast <4 x i32> %xor.i.i to <4 x float>
   %2 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <4 x float> %3 to <8 x half>
   %add = fadd fast <8 x half> %4, %acc.coerce
   ret <8 x half> %add
 }
 
 define dso_local <8 x half> @test7(<8 x half> %acc.coerce, <8 x half> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test7:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %xmm2, %xmm0, %xmm1
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:    vfcmaddcph %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <8 x half> %lhs.coerce.conj to <4 x i32>
   %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %0
   %1 = bitcast <4 x i32> %xor.i.i to <4 x float>
   %2 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <4 x float> %3 to <8 x half>
   %add = fadd fast <8 x half> %acc.coerce, %4
   ret <8 x half> %add
 }
 
 define dso_local <8 x half> @test8(<8 x half> %acc.coerce, <4 x float> %lhs.coerce.conj, <8 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %xmm2, %xmm0, %xmm1
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
+; CHECK-NEXT:    vfcmaddcph %xmm1, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast <4 x float> %lhs.coerce.conj to <4 x i32>
   %xor.i.i = xor <4 x i32> <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>, %0
   %1 = bitcast <4 x i32> %xor.i.i to <4 x float>
   %2 = bitcast <8 x half> %rhs.coerce to <4 x float>
   %3 = tail call fast <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float> %1, <4 x float> %2, <4 x float> zeroinitializer, i8 -1) #2
   %4 = bitcast <4 x float> %3 to <8 x half>
   %add = fadd fast <8 x half> %acc.coerce, %4
   ret <8 x half> %add
 }
 
 define dso_local <32 x half> @test9(<32 x half> %acc.coerce, <8 x i64> %lhs.coerce.conj, <32 x half> %rhs.coerce) local_unnamed_addr #0 {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vfcmaddcph %zmm2, %zmm0, %zmm1
-; CHECK-NEXT:    vmovaps %zmm1, %zmm0
+; CHECK-NEXT:    vfcmaddcph %zmm1, %zmm2, %zmm0
 ; CHECK-NEXT:    retq
 entry:
   %xor1.i = xor <8 x i64> %lhs.coerce.conj, <i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160, i64 -9223372034707292160>
   %0 = bitcast <8 x i64> %xor1.i to <16 x float>
   %1 = bitcast <32 x half> %rhs.coerce to <16 x float>
   %2 = tail call fast <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4) #2
   %3 = bitcast <16 x float> %2 to <32 x half>
   %add = fadd fast <32 x half> %3, %acc.coerce
   ret <32 x half> %add
 }
 
 declare <16 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
 declare <8 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
 declare <4 x float> @llvm.x86.avx512fp16.mask.vfmul.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)