[SDAG] Disable expansion of FMINNUM/FMAXNUM to SELECT_CC for vector operands

[sridhar_gopinath]

Summary

FMINNUM/FMAXNUM is expanded to SELECT_CC when there are no-NaNs. But this expansion is
incorrect for vector operands. This fix disables this expansion for vectors.

[craig.topper]

Why is it incorrect for vectors? Is possible to write a test for this?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (Node->getFlags().hasNoNaNs()) {
     unsigned IEEE2018Op =
         Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
     if (isOperationLegalOrCustom(IEEE2018Op, VT)) {
       return DAG.getNode(IEEE2018Op, dl, VT, Node->getOperand(0),
                          Node->getOperand(1), Node->getFlags());
     }
   }
 
-  // If none of the above worked, but there are no NaNs, then expand to
-  // a compare/select sequence.  This is required for correctness since
-  // InstCombine might have canonicalized a fcmp+select sequence to a
+  // If none of the above worked for scalar operands, but there are no NaNs,
+  // then expand to a compare/select sequence.  This is required for correctness
+  // since InstCombine might have canonicalized a fcmp+select sequence to a
   // FMINNUM/FMAXNUM node.  If we were to fall through to the default
   // expansion to libcall, we might introduce a link-time dependency
   // on libm into a file that originally did not have one.
-  if (Node->getFlags().hasNoNaNs()) {
+  if (!VT.isVector() && Node->getFlags().hasNoNaNs()) {
     ISD::CondCode Pred =
         Node->getOpcode() == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
     SDValue Op1 = Node->getOperand(0);
     SDValue Op2 = Node->getOperand(1);
     SDValue SelCC = DAG.getSelectCC(dl, Op1, Op2, Op1, Op2, Pred);
     // Copy FMF flags, but always set the no-signed-zeros flag
     // as this is implied by the FMINNUM/FMAXNUM semantics.
     SDNodeFlags Flags = Node->getFlags();