[ARM] Fix operands of `Int_eh_sjlj_longjmp`

[xtkoba]

Summary

On Linux, it was made possible by https://reviews.llvm.org/D38253 that __builtin_longjmp can jump between ARM mode and Thumb mode. This was done by restoring the saved frame address to each of r7 and r11, the frame pointer register on Linux in Thumb mode and ARM mode, respectively.

However, there has been revealed a case that __builtin_longjmp from ARM mode does not work. In that case, __builtin_longjmp chooses r7 for the scratch register, trying to branch to the address contained in it, which has already been overwritten by the saved frame address.

This seems to be not easily worked around on user's side. For example, the compiler option -fno-omit-frame-pointer will not prevent r7 from being used as the scratch register, because it is not the frame pointer register in ARM mode.

In the proposed change, Int_eh_sjlj_longjmp is made to use the new register class GPRnofp which excludes the potential frame pointer registers r7 and r11.

[xtkoba]

Diff context extended

[xtkoba]

Test revised

[xtkoba]

Test revised^2

[mstorsjo]

@efriedma Can you have a look at this?

[efriedma]

The general approach here seems fine.

llvm/lib/Target/ARM/ARMInstrInfo.td

5910

I think this addresses the FIXME. Add a comment noting that we're intentionally not defining separate versions of this instruction based on the frame pointer register.

llvm/lib/Target/ARM/ARMRegisterInfo.td

258

Maybe (sub GPR, R7, R11, PC)? Probably doesn't have any practical effect, but just in case.

llvm/test/CodeGen/Thumb/high-reg-clobber.mir

47

Please fix the number "1048585" to actually refer to the intended register class: hGPR.

llvm/lib/Target/ARM/ARMInstrInfo.td

   [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
   hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
   def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
                                    NoItinerary,
                          [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
                                 Requires<[IsARM, NoVFP]>;
 }
 
 // FIXME: Non-IOS version(s)
 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
-    Defs = [ R7, LR, SP ] in {
-def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
+    Defs = [ R7, R11, LR, SP ] in {
+def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPRnofp:$src, GPRnofp:$scratch),
                              NoItinerary,
-                         [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
+                         [(ARMeh_sjlj_longjmp GPRnofp:$src, GPRnofp:$scratch)]>,
                                 Requires<[IsARM]>;
 }
 
 let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in
 def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary,
             [(ARMeh_sjlj_setup_dispatch)]>;
 
 // eh.sjlj.dispatchsetup pseudo-instruction.

llvm/lib/Target/ARM/ARMRegisterInfo.td

def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
   let AltOrders = [(add GPRnoip, GPRnoip), (trunc GPRnoip, 8),
                    (add (trunc GPRnoip, 8), (shl GPRnoip, 8))];
   let AltOrderSelect = [{
       return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
   }];
   let DiagnosticString = "operand must be a register in range [r0, r14]";
 }
 
+// GPRs without potential FPs.  Used by eh_sjlj_longjmp().
+def GPRnofp : RegisterClass<"ARM", [i32], 32, (sub GPR, R7, R11)> {
+  let AltOrders = [(add LR, GPRnofp), (trunc GPRnofp, 7),
+                   (add (trunc GPRnofp, 7), R12, LR, (shl GPRnofp, 7))];
+  let AltOrderSelect = [{
+      return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
+  }];
+  let DiagnosticString = "operand must be a register in range [r0, r15]";
+}
+
 // GPRs without the PC.  Some ARM instructions do not allow the PC in
 // certain operand slots, particularly as the destination.  Primarily
 // useful for disassembly.
 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
   let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8),
                    (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
   let AltOrderSelect = [{
       return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);

llvm/test/CodeGen/Thumb/high-reg-clobber.mir

bb.0.entry:
     liveins: $r0
 
     ; CHECK-LABEL: name: constraint_h
     ; CHECK: liveins: $r0
     ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
     ; CHECK: tSTRspi [[COPY]], %stack.0, 0, 14 /* CC::al */, $noreg
     ; CHECK: [[tLDRspi:%[0-9]+]]:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     ; CHECK: [[COPY1:%[0-9]+]]:hgpr = COPY [[tLDRspi]]
-    ; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, [[COPY1]], 12 /* clobber */, implicit-def early-clobber $r12
+    ; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnofp_and_GPRnopc */, [[COPY1]], 12 /* clobber */, implicit-def early-clobber $r12
     ; CHECK: tBX_RET 14 /* CC::al */, $noreg
     ; FAST-LABEL: name: constraint_h
     ; FAST: liveins: $r0
     ; FAST: tSTRspi killed renamable $r0, %stack.0, 0, 14 /* CC::al */, $noreg
     ; FAST: renamable $r0 = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     ; FAST: renamable $r8 = COPY killed renamable $r0
-    ; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
+    ; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnofp_and_GPRnopc */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
     ; FAST: tBX_RET 14 /* CC::al */, $noreg
     %0:tgpr = COPY $r0
     tSTRspi %0, %stack.0, 0, 14 /* CC::al */, $noreg
     %2:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     %1:hgpr = COPY %2
     INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:hGPR */, %1, 12 /* clobber */, implicit-def early-clobber $r12
     tBX_RET 14 /* CC::al */, $noreg
 
 ...