[SystemZ] Implement memcmp with variable length with CLC.

[jonpa]

Summary

Following the same pattern of memset/memcpy, this patch implements a variable length memcmp with a CLC loop followed by an EXRL instruction.

• For a zero length memcompare, the aghi check against -1 should return a CC that is equivalent to "EQ" also for the memcompare IPM result, which seems reasonable..?

• Hope it's ok to add a CC-def on the EXRL_Pseudo instead of an extra opcode like EXRL_Pseudo_CC...

• emitMemMemVarLen() has for now merely been copied from the memcpy patch (with some minor modification).

• ~1300 less library calls on spec.

Now that benchmarking is in progress for the memcpy patch, could this also be evaluated in parallel at this point?

[jonpa]

Remember to swap the operands for the IPM sequence.

[uweigand]

This LGTM, but it would be good to see some full benchmark results as well.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

MachineBasicBlock *SystemZTargetLowering::emitMemMemWrapper(
   uint64_t SrcDisp = MI.getOperand(3).getImm();
   MachineOperand &LengthMO = MI.getOperand(4);
   uint64_t ImmLength = LengthMO.isImm() ? LengthMO.getImm() : 0;
   Register LenMinus1Reg =
       LengthMO.isReg() ? LengthMO.getReg() : SystemZ::NoRegister;
 
   // When generating more than one CLC, all but the last will need to
   // branch to the end when a difference is found.
-  MachineBasicBlock *EndMBB = (ImmLength > 256 && Opcode == SystemZ::CLC
-                                   ? SystemZ::splitBlockAfter(MI, MBB)
-                                   : nullptr);
+  MachineBasicBlock *EndMBB =
+      (Opcode == SystemZ::CLC &&
+               (ImmLength > 256 || LenMinus1Reg != SystemZ::NoRegister)
 
   // Check for the loop form, in which operand 5 is the trip count.
   if (MI.getNumExplicitOperands() > 5) {
     Register StartCountReg = MI.getOperand(5).getReg();
     bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
 
     auto loadZeroAddress = [&]() -> MachineOperand {
       Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
if (MI.getNumExplicitOperands() > 5) {
     RC = &SystemZ::GR64BitRegClass;
     Register ThisCountReg = MRI.createVirtualRegister(RC);
     Register NextCountReg = MRI.createVirtualRegister(RC);
 
     if (LengthMO.isReg()) {
       AllDoneMBB = SystemZ::splitBlockBefore(MI, MBB);
       StartMBB = SystemZ::emitBlockAfter(MBB);
       LoopMBB = SystemZ::emitBlockAfter(StartMBB);
-      NextMBB = LoopMBB;
-      DoneMBB = SystemZ::emitBlockAfter(LoopMBB);
+      NextMBB = (EndMBB ? SystemZ::emitBlockAfter(LoopMBB) : LoopMBB);
+      DoneMBB = SystemZ::emitBlockAfter(NextMBB);
 
       //  MBB:
       //   # Jump to AllDoneMBB if LenMinus1Reg is -1, or fall thru to StartMBB.
       BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
         .addReg(LenMinus1Reg).addImm(-1);
       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_EQ)
         .addMBB(AllDoneMBB);
if (LengthMO.isReg()) {
       //   illegal value. The number of bytes processed becomes (%LenMinus1Reg &
       //   0xff) + 1.
       // # Fall through to AllDoneMBB.
       Register RemSrcReg  = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
       Register RemDestReg = HaveSingleBase ? RemSrcReg
         : MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
       BuildMI(MBB, DL, TII->get(SystemZ::PHI), RemDestReg)
         .addReg(StartDestReg).addMBB(StartMBB)
-        .addReg(NextDestReg).addMBB(LoopMBB);
+        .addReg(NextDestReg).addMBB(NextMBB);
       if (!HaveSingleBase)
         BuildMI(MBB, DL, TII->get(SystemZ::PHI), RemSrcReg)
           .addReg(StartSrcReg).addMBB(StartMBB)
-          .addReg(NextSrcReg).addMBB(LoopMBB);
+          .addReg(NextSrcReg).addMBB(NextMBB);
       MRI.constrainRegClass(LenMinus1Reg, &SystemZ::ADDR64BitRegClass);
+      MachineInstrBuilder EXRL_MIB =
         BuildMI(MBB, DL, TII->get(SystemZ::EXRL_Pseudo))
           .addImm(Opcode)
           .addReg(LenMinus1Reg)
           .addReg(RemDestReg).addImm(DestDisp)
           .addReg(RemSrcReg).addImm(SrcDisp);
       MBB->addSuccessor(AllDoneMBB);
       MBB = AllDoneMBB;
+      if (EndMBB) {
+        EXRL_MIB.addReg(SystemZ::CC, RegState::ImplicitDefine);
+        MBB->addLiveIn(SystemZ::CC);
+      }
     }
   }
 
   // Handle any remaining bytes with straight-line code.
   while (ImmLength > 0) {
     uint64_t ThisLength = std::min(ImmLength, uint64_t(256));
     // The previous iteration might have created out-of-range displacements.
     // Apply them using LAY if so.
MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
   case SystemZ::OCLoop:
     return emitMemMemWrapper(MI, MBB, SystemZ::OC);
   case SystemZ::XCSequence:
   case SystemZ::XCLoop:
   case SystemZ::XCLoopVarLen:
     return emitMemMemWrapper(MI, MBB, SystemZ::XC);
   case SystemZ::CLCSequence:
   case SystemZ::CLCLoop:
+  case SystemZ::CLCLoopVarLen:
     return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
   case SystemZ::CLSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::CLST);
   case SystemZ::MVSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::MVST);
   case SystemZ::SRSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::SRST);
   case SystemZ::TBEGIN:

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
     def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
                                        imm64:$length),
                            [(set CC, (sequence bdaddr12only:$dest, bdaddr12only:$src,
                                                imm64:$length))]>;
     def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
                                    imm64:$length, GR64:$count256),
                       [(set CC, (loop bdaddr12only:$dest, bdaddr12only:$src,
                                       imm64:$length, GR64:$count256))]>;
+    def LoopVarLen : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
+                                         GR64:$length, GR64:$count256),
+                            [(set CC, (loop bdaddr12only:$dest, bdaddr12only:$src,
+                                            GR64:$length, GR64:$count256))]>;
   }
 }
 
 // Define an instruction that operates on two strings, both terminated
 // by the character in R0.  The instruction processes a CPU-determinated
 // number of bytes at a time and sets CC to 3 if the instruction needs
 // to be repeated.  Also define a pseudo instruction that represents
 // the full loop (the main instruction plus the branch on CC==3).

llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp

 static SDValue emitMemMemVarLen(SelectionDAG &DAG, const SDLoc &DL,
                                 unsigned Loop, SDValue Chain, SDValue Dst,
                                 SDValue Src, SDValue Size) {
   SDValue LenMinus1 = DAG.getNode(ISD::ADD, DL, MVT::i64,
                                   DAG.getZExtOrTrunc(Size, DL, MVT::i64),
                                   DAG.getConstant(-1, DL, MVT::i64));
   SDValue TripC = DAG.getNode(ISD::SRL, DL, MVT::i64, LenMinus1,
                               DAG.getConstant(8, DL, MVT::i64));
-  return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, LenMinus1, TripC);
+  SDVTList VTs = Loop == SystemZISD::CLC_LOOP
+                     ? DAG.getVTList(MVT::i32, MVT::Other)
+                     : DAG.getVTList(MVT::Other);
+  return DAG.getNode(Loop, DL, VTs, Chain, Dst, Src, LenMinus1, TripC);
 }
 
 SDValue SystemZSelectionDAGInfo::EmitTargetCodeForMemcpy(
     SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src,
     SDValue Size, Align Alignment, bool IsVolatile, bool AlwaysInline,
     MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
   if (IsVolatile)
     return SDValue();
SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
                             DAG.getConstant(30, DL, MVT::i32));
   return SRA;
 }
 
 std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(
     SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
     SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo,
     MachinePointerInfo Op2PtrInfo) const {
+  SDValue CCReg;
+  // Swap operands to invert CC == 1 vs. CC == 2 cases.
   if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
     uint64_t Bytes = CSize->getZExtValue();
     assert(Bytes > 0 && "Caller should have handled 0-size case");
-    // Swap operands to invert CC == 1 vs. CC == 2 cases.
-    SDValue CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
-    Chain = CCReg.getValue(1);
-    return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain);
-  }
-  return std::make_pair(SDValue(), SDValue());
-}
+    CCReg = emitCLC(DAG, DL, Chain, Src2, Src1, Bytes);
+  } else
+    CCReg = emitMemMemVarLen(DAG, DL, SystemZISD::CLC_LOOP, Chain, Src2, Src1,
+                             Size);
 
 std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(
     SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src,
     SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const {
   // Use SRST to find the character.  End is its address on success.
   EVT PtrVT = Src.getValueType();
   SDVTList VTs = DAG.getVTList(PtrVT, MVT::i32, MVT::Other);
   Length = DAG.getZExtOrTrunc(Length, DL, PtrVT);

llvm/test/CodeGen/SystemZ/memcmp-01.ll

 ; CHECK: brctg [[COUNT]], [[LOOP]]
 ; CHECK: clc 0(1,%r3), 0(%r2)
 ; CHECK: [[LABEL]]:
 ; CHECK: ipm [[REG:%r[0-5]]]
 ; CHECK: br %r14
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 769)
   ret i32 %res
 }
+
+define i32 @f14(i8 *%src1, i8 *%src2, i64 %Len) {
+; CHECK-LABEL: f14:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    aghi %r4, -1
+; CHECK-NEXT:    cghi %r4, -1
+; CHECK-NEXT:    je .LBB13_5
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    srlg %r0, %r4, 8
+; CHECK-NEXT:    cgije %r0, 0, .LBB13_4
+; CHECK-NEXT:  .LBB13_2: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    clc 0(256,%r3), 0(%r2)
+; CHECK-NEXT:    jlh .LBB13_5
+; CHECK-NEXT:  # %bb.3: # in Loop: Header=BB13_2 Depth=1
+; CHECK-NEXT:    la %r3, 256(%r3)
+; CHECK-NEXT:    la %r2, 256(%r2)
+; CHECK-NEXT:    brctg %r0, .LBB13_2
+; CHECK-NEXT:  .LBB13_4:
+; CHECK-NEXT:    exrl %r4, .Ltmp0
+; CHECK-NEXT:  .LBB13_5:
+; CHECK-NEXT:    ipm %r2
+; CHECK-NEXT:    sll %r2, 2
+; CHECK-NEXT:    sra %r2, 30
+; CHECK-NEXT:    br %r14
+  %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 %Len)
+  ret i32 %res
+}