tsan: use DCHECK instead of CHECK in atomic functions

[dvyukov]

Summary

Atomic functions are semi-hot in profiles.
The CHECKs verify values passed by compiler
and they never fired, so replace them with DCHECKs.

[melver]

Turns out that Clang turns invalid orders into 0==relaxed: https://godbolt.org/z/nrz44zoMn

GCC doesn't seem to do so and happily passes the invalid order to the runtime.

It may still be a valid debugging aid to users if we ever expect Clang to change that. Other than that, one would hope that the incorrect memory order would eventually manifest in a reported data race.

[dvyukov]

In D107373#2922969, @melver wrote:

Turns out that Clang turns invalid orders into 0==relaxed: https://godbolt.org/z/nrz44zoMn

GCC doesn't seem to do so and happily passes the invalid order to the runtime.

It may still be a valid debugging aid to users if we ever expect Clang to change that. Other than that, one would hope that the incorrect memory order would eventually manifest in a reported data race.

Yes, clang now handles this in the compiler. I don't want to introduce runtime overhead only for gcc that is not doing the same.

compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp

 
 using namespace __tsan;
 
 #if !SANITIZER_GO && __TSAN_HAS_INT128
 // Protects emulation of 128-bit atomic operations.
 static StaticSpinMutex mutex128;
 #endif
 
+#if SANITIZER_DEBUG
 static bool IsLoadOrder(morder mo) {
   return mo == mo_relaxed || mo == mo_consume
       || mo == mo_acquire || mo == mo_seq_cst;
 }
 
 static bool IsStoreOrder(morder mo) {
   return mo == mo_relaxed || mo == mo_release || mo == mo_seq_cst;
 }
+#endif
 
 static bool IsReleaseOrder(morder mo) {
   return mo == mo_release || mo == mo_acq_rel || mo == mo_seq_cst;
 }
 
 static bool IsAcquireOrder(morder mo) {
   return mo == mo_consume || mo == mo_acquire
       || mo == mo_acq_rel || mo == mo_seq_cst;
static memory_order to_mo(morder mo) {
   switch (mo) {
   case mo_relaxed: return memory_order_relaxed;
   case mo_consume: return memory_order_consume;
   case mo_acquire: return memory_order_acquire;
   case mo_release: return memory_order_release;
   case mo_acq_rel: return memory_order_acq_rel;
   case mo_seq_cst: return memory_order_seq_cst;
   }
-  CHECK(0);
+  DCHECK(0);
   return memory_order_seq_cst;
 }
 
 template<typename T>
 static T NoTsanAtomicLoad(const volatile T *a, morder mo) {
   return atomic_load(to_atomic(a), to_mo(mo));
 }
 
 #if __TSAN_HAS_INT128 && !SANITIZER_GO
 static a128 NoTsanAtomicLoad(const volatile a128 *a, morder mo) {
   SpinMutexLock lock(&mutex128);
   return *a;
 }
 #endif
 
 template <typename T>
 static T AtomicLoad(ThreadState *thr, uptr pc, const volatile T *a, morder mo) {
-  CHECK(IsLoadOrder(mo));
+  DCHECK(IsLoadOrder(mo));
   // This fast-path is critical for performance.
   // Assume the access is atomic.
   if (!IsAcquireOrder(mo)) {
     MemoryAccess(thr, pc, (uptr)a, AccessSize<T>(),
                  kAccessRead | kAccessAtomic);
     return NoTsanAtomicLoad(a, mo);
   }
   // Don't create sync object if it does not exist yet. For example, an atomic
static void NoTsanAtomicStore(volatile a128 *a, a128 v, morder mo) {
   SpinMutexLock lock(&mutex128);
   *a = v;
 }
 #endif
 
 template <typename T>
 static void AtomicStore(ThreadState *thr, uptr pc, volatile T *a, T v,
                         morder mo) {
-  CHECK(IsStoreOrder(mo));
+  DCHECK(IsStoreOrder(mo));
   MemoryAccess(thr, pc, (uptr)a, AccessSize<T>(), kAccessWrite | kAccessAtomic);
   // This fast-path is critical for performance.
   // Assume the access is atomic.
   // Strictly saying even relaxed store cuts off release sequence,
   // so must reset the clock.
   if (!IsReleaseOrder(mo)) {
     NoTsanAtomicStore(a, v, mo);
     return;

 }
 
 template <typename T>
 static bool AtomicCAS(ThreadState *thr, uptr pc, volatile T *a, T *c, T v,
                       morder mo, morder fmo) {
   // 31.7.2.18: "The failure argument shall not be memory_order_release
   // nor memory_order_acq_rel". LLVM (2021-05) fallbacks to Monotonic
   // (mo_relaxed) when those are used.
-  CHECK(IsLoadOrder(fmo));
+  DCHECK(IsLoadOrder(fmo));
 
   MemoryAccess(thr, pc, (uptr)a, AccessSize<T>(), kAccessWrite | kAccessAtomic);
   if (LIKELY(mo == mo_relaxed && fmo == mo_relaxed)) {
     T cc = *c;
     T pr = func_cas(a, cc, v);
     if (pr == cc)
       return true;
     *c = pr;