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Differential D106969

[NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again
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Authored by jrtc27 on Jul 28 2021, 8:17 AM.

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kiausch
nemanjai
jhibbits
Group Reviewers
Restricted Project
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rG6e8660a7d65a: [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again
Summary

Using split-file does not work with update_llc_test_checks.py. It's also
mostly redundant, as the single and double tests can just use a single
llc and FileCheck invocation for each FPU type using -check-prefixes
rather than -check-prefix, and update_llc_test_checks.py will merge what
it can. Only test_dasmconst needs to be SPE-only and so is pulled out
into its own mall file (rather than using sed to preprocess the file and
keep it commented out for EFPU2, which would work, but is ugly).

As well as cutting down on the number of RUN lines, this also results in
test_fma's CHECK lines being merged for both FPUs.

Diff Detail

Event Timeline

jrtc27 created this revision.Jul 28 2021, 8:17 AM
Herald added a subscriber: shchenz. · View Herald TranscriptJul 28 2021, 8:17 AM
jrtc27 requested review of this revision.Jul 28 2021, 8:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 28 2021, 8:17 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B116705: Diff 362399.Jul 28 2021, 8:17 AM
kiausch accepted this revision.Jul 28 2021, 8:28 AM

Looks good to me!

This revision is now accepted and ready to land.Jul 28 2021, 8:28 AM
This revision was landed with ongoing or failed builds.Jul 28 2021, 9:13 AM
Closed by commit rG6e8660a7d65a: [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again (authored by jrtc27). · Explain Why
This revision was automatically updated to reflect the committed changes.
jrtc27 added a commit: rG6e8660a7d65a: [NFC][PowerPC] Fix spe.ll to work with update_llc_test_checks.py again.

Revision Contents

PathSize
llvm/
test/
CodeGen/
PowerPC/
23 lines
367 lines

Diff 362426

llvm/test/CodeGen/PowerPC/spe-hwdouble.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+spe | FileCheck %s
define i32 @test_dasmconst(double %x) #0 {
; CHECK-LABEL: test_dasmconst:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: evmergelo 3, 3, 4
; CHECK-NEXT: evstdd 3, 8(1)
; CHECK-NEXT: #APP
; CHECK-NEXT: efdctsi 3, 3
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: blr
entry:
%x.addr = alloca double, align 8
store double %x, double* %x.addr, align 8
%0 = load double, double* %x.addr, align 8
%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
ret i32 %1
}
attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/spe.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: split-file %s %t ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \ ; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
; RUN: -mattr=+spe | FileCheck %t/single.ll ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \ ; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
; RUN: -mattr=+spe | FileCheck %t/double.ll -check-prefix=SPE
; RUN: llc -verify-machineinstrs < %t/hwdouble.ll -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+spe | FileCheck %t/hwdouble.ll -check-prefix=SPE
; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+efpu2 | FileCheck %t/single.ll
; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
; RUN: -mattr=+efpu2 | FileCheck %t/double.ll -check-prefix=EFPU2
;--- single.ll
; single tests (identical for -mattr=+spe and -mattr=+efpu2) ; single tests (identical for -mattr=+spe and -mattr=+efpu2)
declare float @llvm.fabs.float(float) declare float @llvm.fabs.float(float)
define float @test_float_abs(float %a) #0 { define float @test_float_abs(float %a) #0 {
; CHECK-LABEL: test_float_abs: ; CHECK-LABEL: test_float_abs:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: efsabs 3, 3 ; CHECK-NEXT: efsabs 3, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
▲ Show 20 Lines • Show All 514 Lines • ▼ Show 20 Linesentry:
store float %x, float* %x.addr, align 8 store float %x, float* %x.addr, align 8
%0 = load float, float* %x.addr, align 8 %0 = load float, float* %x.addr, align 8
%1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0) %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
ret i32 %1 ret i32 %1
; Check that it's not loading a double ; Check that it's not loading a double
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
;--- double.ll
; Double tests ; Double tests
; results depend on -mattr=+spe or -mattr=+efpu2 ; results depend on -mattr=+spe or -mattr=+efpu2
define float @test_dtos(double %a) #0 { define float @test_dtos(double %a) #0 {
; SPE-LABEL: test_dtos: ; SPE-LABEL: test_dtos:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efscfd 3, 3 ; SPE-NEXT: efscfd 3, 3
▲ Show 20 Lines • Show All 213 Lines • ▼ Show 20 Lines
; SPE-LABEL: test_dcmpuno: ; SPE-LABEL: test_dcmpuno:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: li 7, 1 ; SPE-NEXT: li 7, 1
; SPE-NEXT: efdcmpeq 0, 3, 3 ; SPE-NEXT: efdcmpeq 0, 3, 3
; SPE-NEXT: efdcmpeq 1, 5, 5 ; SPE-NEXT: efdcmpeq 1, 5, 5
; SPE-NEXT: crand 20, 5, 1 ; SPE-NEXT: crand 20, 5, 1
; SPE-NEXT: bc 12, 20, .LBB9_2 ; SPE-NEXT: bc 12, 20, .LBB35_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0 ; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB9_2: # %entry ; SPE-NEXT: .LBB35_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpuno: ; EFPU2-LABEL: test_dcmpuno:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
Show All 14 Lines
; SPE-LABEL: test_dcmpord: ; SPE-LABEL: test_dcmpord:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6 ; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: li 7, 1 ; SPE-NEXT: li 7, 1
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: efdcmpeq 1, 3, 3 ; SPE-NEXT: efdcmpeq 1, 3, 3
; SPE-NEXT: crnand 20, 5, 1 ; SPE-NEXT: crnand 20, 5, 1
; SPE-NEXT: bc 12, 20, .LBB10_2 ; SPE-NEXT: bc 12, 20, .LBB36_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0 ; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB10_2: # %entry ; SPE-NEXT: .LBB36_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpord: ; EFPU2-LABEL: test_dcmpord:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
Show All 11 Lines
define i32 @test_dcmpgt(double %a, double %b) #0 { define i32 @test_dcmpgt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpgt: ; SPE-LABEL: test_dcmpgt:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5 ; SPE-NEXT: efdcmpgt 0, 3, 5
; SPE-NEXT: ble 0, .LBB11_2 ; SPE-NEXT: ble 0, .LBB37_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB11_3 ; SPE-NEXT: b .LBB37_3
; SPE-NEXT: .LBB11_2: # %fa ; SPE-NEXT: .LBB37_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB11_3: # %ret ; SPE-NEXT: .LBB37_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpgt: ; EFPU2-LABEL: test_dcmpgt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 1 ; EFPU2-NEXT: cmpwi 3, 1
; EFPU2-NEXT: blt 0, .LBB11_2 ; EFPU2-NEXT: blt 0, .LBB37_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB11_3 ; EFPU2-NEXT: b .LBB37_3
; EFPU2-NEXT: .LBB11_2: # %fa ; EFPU2-NEXT: .LBB37_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB11_3: # %ret ; EFPU2-NEXT: .LBB37_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
Show All 12 Lines
define i32 @test_dcmpugt(double %a, double %b) #0 { define i32 @test_dcmpugt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpugt: ; SPE-LABEL: test_dcmpugt:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6 ; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: bc 4, 1, .LBB12_4 ; SPE-NEXT: bc 4, 1, .LBB38_4
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpeq 0, 3, 3 ; SPE-NEXT: efdcmpeq 0, 3, 3
; SPE-NEXT: bc 4, 1, .LBB12_4 ; SPE-NEXT: bc 4, 1, .LBB38_4
; SPE-NEXT: # %bb.2: # %entry ; SPE-NEXT: # %bb.2: # %entry
; SPE-NEXT: efdcmpgt 0, 3, 4 ; SPE-NEXT: efdcmpgt 0, 3, 4
; SPE-NEXT: bc 12, 1, .LBB12_4 ; SPE-NEXT: bc 12, 1, .LBB38_4
; SPE-NEXT: # %bb.3: # %fa ; SPE-NEXT: # %bb.3: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: b .LBB12_5 ; SPE-NEXT: b .LBB38_5
; SPE-NEXT: .LBB12_4: # %tr ; SPE-NEXT: .LBB38_4: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: .LBB12_5: # %ret ; SPE-NEXT: .LBB38_5: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpugt: ; EFPU2-LABEL: test_dcmpugt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ledf2 ; EFPU2-NEXT: bl __ledf2
; EFPU2-NEXT: cmpwi 3, 1 ; EFPU2-NEXT: cmpwi 3, 1
; EFPU2-NEXT: blt 0, .LBB12_2 ; EFPU2-NEXT: blt 0, .LBB38_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB12_3 ; EFPU2-NEXT: b .LBB38_3
; EFPU2-NEXT: .LBB12_2: # %fa ; EFPU2-NEXT: .LBB38_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB12_3: # %ret ; EFPU2-NEXT: .LBB38_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
Show All 12 Lines
define i32 @test_dcmple(double %a, double %b) #0 { define i32 @test_dcmple(double %a, double %b) #0 {
; SPE-LABEL: test_dcmple: ; SPE-LABEL: test_dcmple:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5 ; SPE-NEXT: efdcmpgt 0, 3, 5
; SPE-NEXT: bgt 0, .LBB13_2 ; SPE-NEXT: bgt 0, .LBB39_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB13_3 ; SPE-NEXT: b .LBB39_3
; SPE-NEXT: .LBB13_2: # %fa ; SPE-NEXT: .LBB39_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB13_3: # %ret ; SPE-NEXT: .LBB39_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmple: ; EFPU2-LABEL: test_dcmple:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bgt 0, .LBB13_2 ; EFPU2-NEXT: bgt 0, .LBB39_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB13_3 ; EFPU2-NEXT: b .LBB39_3
; EFPU2-NEXT: .LBB13_2: # %fa ; EFPU2-NEXT: .LBB39_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB13_3: # %ret ; EFPU2-NEXT: .LBB39_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
Show All 12 Lines
define i32 @test_dcmpule(double %a, double %b) #0 { define i32 @test_dcmpule(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpule: ; SPE-LABEL: test_dcmpule:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpgt 0, 3, 5 ; SPE-NEXT: efdcmpgt 0, 3, 5
; SPE-NEXT: bgt 0, .LBB14_2 ; SPE-NEXT: bgt 0, .LBB40_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB14_3 ; SPE-NEXT: b .LBB40_3
; SPE-NEXT: .LBB14_2: # %fa ; SPE-NEXT: .LBB40_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB14_3: # %ret ; SPE-NEXT: .LBB40_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpule: ; EFPU2-LABEL: test_dcmpule:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gtdf2 ; EFPU2-NEXT: bl __gtdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bgt 0, .LBB14_2 ; EFPU2-NEXT: bgt 0, .LBB40_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB14_3 ; EFPU2-NEXT: b .LBB40_3
; EFPU2-NEXT: .LBB14_2: # %fa ; EFPU2-NEXT: .LBB40_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB14_3: # %ret ; EFPU2-NEXT: .LBB40_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
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; The type of comparison found in C's if (x == y) ; The type of comparison found in C's if (x == y)
define i32 @test_dcmpeq(double %a, double %b) #0 { define i32 @test_dcmpeq(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpeq: ; SPE-LABEL: test_dcmpeq:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpeq 0, 3, 5 ; SPE-NEXT: efdcmpeq 0, 3, 5
; SPE-NEXT: ble 0, .LBB15_2 ; SPE-NEXT: ble 0, .LBB41_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB15_3 ; SPE-NEXT: b .LBB41_3
; SPE-NEXT: .LBB15_2: # %fa ; SPE-NEXT: .LBB41_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB15_3: # %ret ; SPE-NEXT: .LBB41_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpeq: ; EFPU2-LABEL: test_dcmpeq:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __nedf2 ; EFPU2-NEXT: bl __nedf2
; EFPU2-NEXT: cmplwi 3, 0 ; EFPU2-NEXT: cmplwi 3, 0
; EFPU2-NEXT: bne 0, .LBB15_2 ; EFPU2-NEXT: bne 0, .LBB41_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB15_3 ; EFPU2-NEXT: b .LBB41_3
; EFPU2-NEXT: .LBB15_2: # %fa ; EFPU2-NEXT: .LBB41_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB15_3: # %ret ; EFPU2-NEXT: .LBB41_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
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define i32 @test_dcmpueq(double %a, double %b) #0 { define i32 @test_dcmpueq(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpueq: ; SPE-LABEL: test_dcmpueq:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: bc 12, 1, .LBB16_3 ; SPE-NEXT: bc 12, 1, .LBB42_3
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpgt 0, 3, 5 ; SPE-NEXT: efdcmpgt 0, 3, 5
; SPE-NEXT: bc 12, 1, .LBB16_3 ; SPE-NEXT: bc 12, 1, .LBB42_3
; SPE-NEXT: # %bb.2: # %tr ; SPE-NEXT: # %bb.2: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB16_4 ; SPE-NEXT: b .LBB42_4
; SPE-NEXT: .LBB16_3: # %fa ; SPE-NEXT: .LBB42_3: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB16_4: # %ret ; SPE-NEXT: .LBB42_4: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpueq: ; EFPU2-LABEL: test_dcmpueq:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
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; EFPU2-NEXT: mr 30, 6 ; EFPU2-NEXT: mr 30, 6
; EFPU2-NEXT: bl __eqdf2 ; EFPU2-NEXT: bl __eqdf2
; EFPU2-NEXT: cmpwi 2, 3, 0 ; EFPU2-NEXT: cmpwi 2, 3, 0
; EFPU2-NEXT: mr 3, 27 ; EFPU2-NEXT: mr 3, 27
; EFPU2-NEXT: mr 4, 28 ; EFPU2-NEXT: mr 4, 28
; EFPU2-NEXT: mr 5, 29 ; EFPU2-NEXT: mr 5, 29
; EFPU2-NEXT: mr 6, 30 ; EFPU2-NEXT: mr 6, 30
; EFPU2-NEXT: bl __unorddf2 ; EFPU2-NEXT: bl __unorddf2
; EFPU2-NEXT: bc 12, 10, .LBB16_3 ; EFPU2-NEXT: bc 12, 10, .LBB42_3
; EFPU2-NEXT: # %bb.1: # %entry ; EFPU2-NEXT: # %bb.1: # %entry
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: bc 4, 2, .LBB16_3 ; EFPU2-NEXT: bc 4, 2, .LBB42_3
; EFPU2-NEXT: # %bb.2: # %fa ; EFPU2-NEXT: # %bb.2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: b .LBB16_4 ; EFPU2-NEXT: b .LBB42_4
; EFPU2-NEXT: .LBB16_3: # %tr ; EFPU2-NEXT: .LBB42_3: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: .LBB16_4: # %ret ; EFPU2-NEXT: .LBB42_4: # %ret
; EFPU2-NEXT: stw 3, 20(1) ; EFPU2-NEXT: stw 3, 20(1)
; EFPU2-NEXT: lwz 3, 20(1) ; EFPU2-NEXT: lwz 3, 20(1)
; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
; EFPU2-NEXT: lwz 12, 72(1) ; EFPU2-NEXT: lwz 12, 72(1)
; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
; EFPU2-NEXT: mtcrf 32, 12 # cr2 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
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; SPE-LABEL: test_dcmpne: ; SPE-LABEL: test_dcmpne:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: li 7, 1 ; SPE-NEXT: li 7, 1
; SPE-NEXT: efdcmplt 0, 3, 5 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: efdcmpgt 1, 3, 5 ; SPE-NEXT: efdcmpgt 1, 3, 5
; SPE-NEXT: crnor 20, 5, 1 ; SPE-NEXT: crnor 20, 5, 1
; SPE-NEXT: bc 12, 20, .LBB17_2 ; SPE-NEXT: bc 12, 20, .LBB43_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0 ; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB17_2: # %entry ; SPE-NEXT: .LBB43_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpne: ; EFPU2-LABEL: test_dcmpne:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -96(1) ; EFPU2-NEXT: stwu 1, -96(1)
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; EFPU2-NEXT: bl __eqdf2 ; EFPU2-NEXT: bl __eqdf2
; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
; EFPU2-NEXT: li 4, 1 ; EFPU2-NEXT: li 4, 1
; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
; EFPU2-NEXT: crorc 20, 2, 10 ; EFPU2-NEXT: crorc 20, 2, 10
; EFPU2-NEXT: lwz 12, 72(1) ; EFPU2-NEXT: lwz 12, 72(1)
; EFPU2-NEXT: bc 12, 20, .LBB17_2 ; EFPU2-NEXT: bc 12, 20, .LBB43_2
; EFPU2-NEXT: # %bb.1: # %entry ; EFPU2-NEXT: # %bb.1: # %entry
; EFPU2-NEXT: ori 3, 4, 0 ; EFPU2-NEXT: ori 3, 4, 0
; EFPU2-NEXT: b .LBB17_3 ; EFPU2-NEXT: b .LBB43_3
; EFPU2-NEXT: .LBB17_2: # %entry ; EFPU2-NEXT: .LBB43_2: # %entry
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB17_3: # %entry ; EFPU2-NEXT: .LBB43_3: # %entry
; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload ; EFPU2-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
; EFPU2-NEXT: mtcrf 32, 12 # cr2 ; EFPU2-NEXT: mtcrf 32, 12 # cr2
; EFPU2-NEXT: lwz 30, 88(1) # 4-byte Folded Reload ; EFPU2-NEXT: lwz 30, 88(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 29, 84(1) # 4-byte Folded Reload ; EFPU2-NEXT: lwz 29, 84(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 28, 80(1) # 4-byte Folded Reload ; EFPU2-NEXT: lwz 28, 80(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 27, 76(1) # 4-byte Folded Reload ; EFPU2-NEXT: lwz 27, 76(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 0, 100(1) ; EFPU2-NEXT: lwz 0, 100(1)
; EFPU2-NEXT: addi 1, 1, 96 ; EFPU2-NEXT: addi 1, 1, 96
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = fcmp one double %a, %b %r = fcmp one double %a, %b
ret i1 %r ret i1 %r
} }
define i32 @test_dcmpune(double %a, double %b) #0 { define i32 @test_dcmpune(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpune: ; SPE-LABEL: test_dcmpune:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmpeq 0, 3, 5 ; SPE-NEXT: efdcmpeq 0, 3, 5
; SPE-NEXT: bgt 0, .LBB18_2 ; SPE-NEXT: bgt 0, .LBB44_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB18_3 ; SPE-NEXT: b .LBB44_3
; SPE-NEXT: .LBB18_2: # %fa ; SPE-NEXT: .LBB44_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB18_3: # %ret ; SPE-NEXT: .LBB44_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpune: ; EFPU2-LABEL: test_dcmpune:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __eqdf2 ; EFPU2-NEXT: bl __eqdf2
; EFPU2-NEXT: cmplwi 3, 0 ; EFPU2-NEXT: cmplwi 3, 0
; EFPU2-NEXT: beq 0, .LBB18_2 ; EFPU2-NEXT: beq 0, .LBB44_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB18_3 ; EFPU2-NEXT: b .LBB44_3
; EFPU2-NEXT: .LBB18_2: # %fa ; EFPU2-NEXT: .LBB44_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB18_3: # %ret ; EFPU2-NEXT: .LBB44_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
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define i32 @test_dcmplt(double %a, double %b) #0 { define i32 @test_dcmplt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmplt: ; SPE-LABEL: test_dcmplt:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: ble 0, .LBB19_2 ; SPE-NEXT: ble 0, .LBB45_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB19_3 ; SPE-NEXT: b .LBB45_3
; SPE-NEXT: .LBB19_2: # %fa ; SPE-NEXT: .LBB45_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB19_3: # %ret ; SPE-NEXT: .LBB45_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmplt: ; EFPU2-LABEL: test_dcmplt:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ltdf2 ; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, -1 ; EFPU2-NEXT: cmpwi 3, -1
; EFPU2-NEXT: bgt 0, .LBB19_2 ; EFPU2-NEXT: bgt 0, .LBB45_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB19_3 ; EFPU2-NEXT: b .LBB45_3
; EFPU2-NEXT: .LBB19_2: # %fa ; EFPU2-NEXT: .LBB45_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB19_3: # %ret ; EFPU2-NEXT: .LBB45_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
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define i32 @test_dcmpult(double %a, double %b) #0 { define i32 @test_dcmpult(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpult: ; SPE-LABEL: test_dcmpult:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6 ; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: bc 4, 1, .LBB20_4 ; SPE-NEXT: bc 4, 1, .LBB46_4
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpeq 0, 3, 3 ; SPE-NEXT: efdcmpeq 0, 3, 3
; SPE-NEXT: bc 4, 1, .LBB20_4 ; SPE-NEXT: bc 4, 1, .LBB46_4
; SPE-NEXT: # %bb.2: # %entry ; SPE-NEXT: # %bb.2: # %entry
; SPE-NEXT: efdcmplt 0, 3, 4 ; SPE-NEXT: efdcmplt 0, 3, 4
; SPE-NEXT: bc 12, 1, .LBB20_4 ; SPE-NEXT: bc 12, 1, .LBB46_4
; SPE-NEXT: # %bb.3: # %fa ; SPE-NEXT: # %bb.3: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: b .LBB20_5 ; SPE-NEXT: b .LBB46_5
; SPE-NEXT: .LBB20_4: # %tr ; SPE-NEXT: .LBB46_4: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: .LBB20_5: # %ret ; SPE-NEXT: .LBB46_5: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpult: ; EFPU2-LABEL: test_dcmpult:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __gedf2 ; EFPU2-NEXT: bl __gedf2
; EFPU2-NEXT: cmpwi 3, -1 ; EFPU2-NEXT: cmpwi 3, -1
; EFPU2-NEXT: bgt 0, .LBB20_2 ; EFPU2-NEXT: bgt 0, .LBB46_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB20_3 ; EFPU2-NEXT: b .LBB46_3
; EFPU2-NEXT: .LBB20_2: # %fa ; EFPU2-NEXT: .LBB46_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB20_3: # %ret ; EFPU2-NEXT: .LBB46_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
Show All 16 Lines
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6 ; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: li 7, 1 ; SPE-NEXT: li 7, 1
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: efdcmpeq 0, 4, 4
; SPE-NEXT: efdcmpeq 1, 3, 3 ; SPE-NEXT: efdcmpeq 1, 3, 3
; SPE-NEXT: efdcmplt 5, 3, 4 ; SPE-NEXT: efdcmplt 5, 3, 4
; SPE-NEXT: crand 24, 5, 1 ; SPE-NEXT: crand 24, 5, 1
; SPE-NEXT: crorc 20, 21, 24 ; SPE-NEXT: crorc 20, 21, 24
; SPE-NEXT: bc 12, 20, .LBB21_2 ; SPE-NEXT: bc 12, 20, .LBB47_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0 ; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB21_2: # %entry ; SPE-NEXT: .LBB47_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpge: ; EFPU2-LABEL: test_dcmpge:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
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define i32 @test_dcmpuge(double %a, double %b) #0 { define i32 @test_dcmpuge(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpuge: ; SPE-LABEL: test_dcmpuge:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: efdcmplt 0, 3, 5 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: bgt 0, .LBB22_2 ; SPE-NEXT: bgt 0, .LBB48_2
; SPE-NEXT: # %bb.1: # %tr ; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB22_3 ; SPE-NEXT: b .LBB48_3
; SPE-NEXT: .LBB22_2: # %fa ; SPE-NEXT: .LBB48_2: # %fa
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB22_3: # %ret ; SPE-NEXT: .LBB48_3: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpuge: ; EFPU2-LABEL: test_dcmpuge:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1) ; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -16(1) ; EFPU2-NEXT: stwu 1, -16(1)
; EFPU2-NEXT: bl __ltdf2 ; EFPU2-NEXT: bl __ltdf2
; EFPU2-NEXT: cmpwi 3, 0 ; EFPU2-NEXT: cmpwi 3, 0
; EFPU2-NEXT: blt 0, .LBB22_2 ; EFPU2-NEXT: blt 0, .LBB48_2
; EFPU2-NEXT: # %bb.1: # %tr ; EFPU2-NEXT: # %bb.1: # %tr
; EFPU2-NEXT: li 3, 1 ; EFPU2-NEXT: li 3, 1
; EFPU2-NEXT: b .LBB22_3 ; EFPU2-NEXT: b .LBB48_3
; EFPU2-NEXT: .LBB22_2: # %fa ; EFPU2-NEXT: .LBB48_2: # %fa
; EFPU2-NEXT: li 3, 0 ; EFPU2-NEXT: li 3, 0
; EFPU2-NEXT: .LBB22_3: # %ret ; EFPU2-NEXT: .LBB48_3: # %ret
; EFPU2-NEXT: stw 3, 12(1) ; EFPU2-NEXT: stw 3, 12(1)
; EFPU2-NEXT: lwz 3, 12(1) ; EFPU2-NEXT: lwz 3, 12(1)
; EFPU2-NEXT: lwz 0, 20(1) ; EFPU2-NEXT: lwz 0, 20(1)
; EFPU2-NEXT: addi 1, 1, 16 ; EFPU2-NEXT: addi 1, 1, 16
; EFPU2-NEXT: mtlr 0 ; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%r = alloca i32, align 4 %r = alloca i32, align 4
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} }
define double @test_dselect(double %a, double %b, i1 %c) #0 { define double @test_dselect(double %a, double %b, i1 %c) #0 {
; SPE-LABEL: test_dselect: ; SPE-LABEL: test_dselect:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: andi. 7, 7, 1 ; SPE-NEXT: andi. 7, 7, 1
; SPE-NEXT: evmergelo 5, 5, 6 ; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 4, 3, 4 ; SPE-NEXT: evmergelo 4, 3, 4
; SPE-NEXT: bc 12, 1, .LBB23_2 ; SPE-NEXT: bc 12, 1, .LBB49_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: evor 4, 5, 5 ; SPE-NEXT: evor 4, 5, 5
; SPE-NEXT: .LBB23_2: # %entry ; SPE-NEXT: .LBB49_2: # %entry
; SPE-NEXT: evmergehi 3, 4, 4 ; SPE-NEXT: evmergehi 3, 4, 4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4 ; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3 ; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dselect: ; EFPU2-LABEL: test_dselect:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: andi. 7, 7, 1 ; EFPU2-NEXT: andi. 7, 7, 1
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; EFPU2-NEXT: blr ; EFPU2-NEXT: blr
entry: entry:
%v = sitofp i32 %a to double %v = sitofp i32 %a to double
ret double %v ret double %v
} }
declare double @test_spill_spe_regs(double, double); declare double @test_spill_spe_regs(double, double);
define dso_local void @test_func2() #0 { define dso_local void @test_func2() #0 {
; SPE-LABEL: test_func2: ; CHECK-LABEL: test_func2:
; SPE: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; SPE-NEXT: blr ; CHECK-NEXT: blr
;
; EFPU2-LABEL: test_func2:
; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: blr
entry: entry:
ret void ret void
} }
declare void @test_memset(i8* nocapture writeonly, i8, i32, i1) declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
@global_var1 = global i32 0, align 4 @global_var1 = global i32 0, align 4
define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) #0 { define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) #0 {
; SPE-LABEL: test_spill: ; SPE-LABEL: test_spill:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr 0 ; SPE-NEXT: mflr 0
; SPE-NEXT: stw 0, 4(1) ; SPE-NEXT: stw 0, 4(1)
; SPE-NEXT: stwu 1, -352(1) ; SPE-NEXT: stwu 1, -352(1)
; SPE-NEXT: li 5, 256 ; SPE-NEXT: li 5, 256
; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill ; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill
; SPE-NEXT: li 5, 264 ; SPE-NEXT: li 5, 264
; SPE-NEXT: evstddx 31, 1, 5 # 8-byte Folded Spill ; SPE-NEXT: evstddx 31, 1, 5 # 8-byte Folded Spill
; SPE-NEXT: li 5, .LCPI29_0@l ; SPE-NEXT: li 5, .LCPI55_0@l
; SPE-NEXT: lis 6, .LCPI29_0@ha ; SPE-NEXT: lis 6, .LCPI55_0@ha
; SPE-NEXT: evlddx 5, 6, 5 ; SPE-NEXT: evlddx 5, 6, 5
; SPE-NEXT: stw 14, 280(1) # 4-byte Folded Spill ; SPE-NEXT: stw 14, 280(1) # 4-byte Folded Spill
; SPE-NEXT: stw 15, 284(1) # 4-byte Folded Spill ; SPE-NEXT: stw 15, 284(1) # 4-byte Folded Spill
; SPE-NEXT: stw 16, 288(1) # 4-byte Folded Spill ; SPE-NEXT: stw 16, 288(1) # 4-byte Folded Spill
; SPE-NEXT: stw 17, 292(1) # 4-byte Folded Spill ; SPE-NEXT: stw 17, 292(1) # 4-byte Folded Spill
; SPE-NEXT: stw 18, 296(1) # 4-byte Folded Spill ; SPE-NEXT: stw 18, 296(1) # 4-byte Folded Spill
; SPE-NEXT: stw 19, 300(1) # 4-byte Folded Spill ; SPE-NEXT: stw 19, 300(1) # 4-byte Folded Spill
; SPE-NEXT: stw 20, 304(1) # 4-byte Folded Spill ; SPE-NEXT: stw 20, 304(1) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Linesentry:
br label %return br label %return
return: return:
ret double %1 ret double %1
} }
define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 { define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
; SPE-LABEL: test_fma: ; CHECK-LABEL: test_fma:
; SPE: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; SPE-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; SPE-NEXT: stw 0, 4(1) ; CHECK-NEXT: stw 0, 4(1)
; SPE-NEXT: stwu 1, -48(1) ; CHECK-NEXT: stwu 1, -48(1)
; SPE-NEXT: cmpwi 3, 1 ; CHECK-NEXT: cmpwi 3, 1
; SPE-NEXT: stw 29, 36(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 29, 36(1) # 4-byte Folded Spill
; SPE-NEXT: stw 30, 40(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 30, 40(1) # 4-byte Folded Spill
; SPE-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill ; CHECK-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
; SPE-NEXT: blt 0, .LBB30_3 ; CHECK-NEXT: blt 0, .LBB56_3
; SPE-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: # %bb.1: # %for.body.preheader
; SPE-NEXT: mr 30, 3 ; CHECK-NEXT: mr 30, 3
; SPE-NEXT: li 29, 0 ; CHECK-NEXT: li 29, 0
; SPE-NEXT: # implicit-def: $r5 ; CHECK-NEXT: # implicit-def: $r5
; SPE-NEXT: .LBB30_2: # %for.body ; CHECK-NEXT: .LBB56_2: # %for.body
; SPE-NEXT: # ; CHECK-NEXT: #
; SPE-NEXT: efscfsi 3, 29 ; CHECK-NEXT: efscfsi 3, 29
; SPE-NEXT: mr 4, 3 ; CHECK-NEXT: mr 4, 3
; SPE-NEXT: bl fmaf ; CHECK-NEXT: bl fmaf
; SPE-NEXT: addi 29, 29, 1 ; CHECK-NEXT: addi 29, 29, 1
; SPE-NEXT: cmplw 30, 29 ; CHECK-NEXT: cmplw 30, 29
; SPE-NEXT: mr 5, 3 ; CHECK-NEXT: mr 5, 3
; SPE-NEXT: bne 0, .LBB30_2 ; CHECK-NEXT: bne 0, .LBB56_2
; SPE-NEXT: b .LBB30_4 ; CHECK-NEXT: b .LBB56_4
; SPE-NEXT: .LBB30_3: ; CHECK-NEXT: .LBB56_3:
; SPE-NEXT: # implicit-def: $r5 ; CHECK-NEXT: # implicit-def: $r5
; SPE-NEXT: .LBB30_4: # %for.cond.cleanup ; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup
; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload ; CHECK-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
; SPE-NEXT: mr 3, 5 ; CHECK-NEXT: mr 3, 5
; SPE-NEXT: evldd 29, 8(1) # 8-byte Folded Reload ; CHECK-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
; SPE-NEXT: lwz 30, 40(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
; SPE-NEXT: lwz 29, 36(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
; SPE-NEXT: lwz 0, 52(1) ; CHECK-NEXT: lwz 0, 52(1)
; SPE-NEXT: addi 1, 1, 48 ; CHECK-NEXT: addi 1, 1, 48
; SPE-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; SPE-NEXT: blr ; CHECK-NEXT: blr
;
; EFPU2-LABEL: test_fma:
; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0
; EFPU2-NEXT: stw 0, 4(1)
; EFPU2-NEXT: stwu 1, -48(1)
; EFPU2-NEXT: cmpwi 3, 1
; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill
; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill
; EFPU2-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill
; EFPU2-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
; EFPU2-NEXT: blt 0, .LBB30_3
; EFPU2-NEXT: # %bb.1: # %for.body.preheader
; EFPU2-NEXT: mr 30, 3
; EFPU2-NEXT: li 29, 0
; EFPU2-NEXT: # implicit-def: $r5
; EFPU2-NEXT: .LBB30_2: # %for.body
; EFPU2-NEXT: #
; EFPU2-NEXT: efscfsi 3, 29
; EFPU2-NEXT: mr 4, 3
; EFPU2-NEXT: bl fmaf
; EFPU2-NEXT: addi 29, 29, 1
; EFPU2-NEXT: cmplw 30, 29
; EFPU2-NEXT: mr 5, 3
; EFPU2-NEXT: bne 0, .LBB30_2
; EFPU2-NEXT: b .LBB30_4
; EFPU2-NEXT: .LBB30_3:
; EFPU2-NEXT: # implicit-def: $r5
; EFPU2-NEXT: .LBB30_4: # %for.cond.cleanup
; EFPU2-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
; EFPU2-NEXT: mr 3, 5
; EFPU2-NEXT: evldd 29, 8(1) # 8-byte Folded Reload
; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
; EFPU2-NEXT: lwz 0, 52(1)
; EFPU2-NEXT: addi 1, 1, 48
; EFPU2-NEXT: mtlr 0
; EFPU2-NEXT: blr
entry: entry:
%cmp8 = icmp sgt i32 %d, 0 %cmp8 = icmp sgt i32 %d, 0
br i1 %cmp8, label %for.body, label %for.cond.cleanup br i1 %cmp8, label %for.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.body, %entry for.cond.cleanup: ; preds = %for.body, %entry
%e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ] %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]
ret float %e.0.lcssa ret float %e.0.lcssa
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Linesentry:
%h = call i32 @foo(double %conv) %h = call i32 @foo(double %conv)
%n = sitofp i32 %3 to double %n = sitofp i32 %3 to double
%k = fmul double %g, %n %k = fmul double %g, %n
%l = fptrunc double %k to float %l = fptrunc double %k to float
store float %l, float* undef store float %l, float* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
;--- hwdouble.ll
; split into separate file because the efd* instructions are invalid on efpu2
define i32 @test_dasmconst(double %x) #0 {
; SPE-LABEL: test_dasmconst:
; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evstdd 3, 8(1)
; SPE-NEXT: #APP
; SPE-NEXT: efdctsi 3, 3
; SPE-NEXT: #NO_APP
; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr
entry:
%x.addr = alloca double, align 8
store double %x, double* %x.addr, align 8
%0 = load double, double* %x.addr, align 8
%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
ret i32 %1
}
attributes #0 = { nounwind }