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Differential D106603

[PowerPC] Add implicit-def RM to instructions mtfsb[01]
ClosedPublic

Authored by lei on Jul 22 2021, 2:53 PM.

Details

Reviewers
nemanjai
ZhangKang
power-llvm-team
Commits
rG2d788959edda: [PowerPC] Add implicit-def RM to instructions mtfsb[01]
Summary

This is a followup patch for D105930 to add implicit-def of RM for
mtfsb[01] instructions as per review comments.

Diff Detail

Event Timeline

lei created this revision.Jul 22 2021, 2:53 PM
Herald added subscribers: shchenz, hiraditya. · View Herald TranscriptJul 22 2021, 2:53 PM
lei requested review of this revision.Jul 22 2021, 2:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2021, 2:53 PM
Harbormaster completed remote builds in B115705: Diff 360988.Jul 22 2021, 5:35 PM
nemanjai accepted this revision.Jul 26 2021, 4:22 AM

LGTM. Thanks.

This revision is now accepted and ready to land.Jul 26 2021, 4:22 AM
This revision was landed with ongoing or failed builds.Jul 26 2021, 12:07 PM
Closed by commit rG2d788959edda: [PowerPC] Add implicit-def RM to instructions mtfsb[01] (authored by lei). · Explain Why
This revision was automatically updated to reflect the committed changes.
lei added a commit: rG2d788959edda: [PowerPC] Add implicit-def RM to instructions mtfsb[01].

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
2 lines
test/
CodeGen/
PowerPC/
10 lines

Diff 361748

llvm/lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 3,083 Lines • ▼ Show 20 Lines def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
[(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>;
} }
// The above pseudo gets expanded to make use of the following instructions // The above pseudo gets expanded to make use of the following instructions
// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def // When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def
// RM should be set. // RM should be set.
let hasSideEffects = 1 in { let hasSideEffects = 1, Defs = [RM] in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
"mtfsb0 $FM", IIC_IntMTFSB0, "mtfsb0 $FM", IIC_IntMTFSB0,
[(int_ppc_mtfsb0 timm:$FM)]>, [(int_ppc_mtfsb0 timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
"mtfsb1 $FM", IIC_IntMTFSB0, "mtfsb1 $FM", IIC_IntMTFSB0,
[(int_ppc_mtfsb1 timm:$FM)]>, [(int_ppc_mtfsb1 timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU; PPC970_DGroup_Single, PPC970_Unit_FPU;
▲ Show 20 Lines • Show All 2,409 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mtfsb0 30 ; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: fadd 1, 2, 1 ; CHECK-NEXT: fadd 1, 2, 1
; CHECK-NEXT: mtfsf 1, 0 ; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: fctiwz 0, 1 ; CHECK-NEXT: fctiwz 0, 1
; CHECK-NEXT: stfd 0, 96(1) ; CHECK-NEXT: stfd 0, 96(1)
; CHECK-NEXT: mffs 0 ; CHECK-NEXT: mffs 0
; CHECK-NEXT: mtfsb1 31 ; CHECK-NEXT: mtfsb1 31
; CHECK-NEXT: lis 3, .LCPI0_0@ha ; CHECK-NEXT: lis 3, .LCPI0_0@ha
; CHECK-NEXT: lfs 2, .LCPI0_0@l(3) ; CHECK-NEXT: lfs 1, .LCPI0_0@l(3)
; CHECK-NEXT: mtfsb0 30 ; CHECK-NEXT: mtfsb0 30
; CHECK-NEXT: lis 3, .LCPI0_1@ha ; CHECK-NEXT: lis 3, .LCPI0_1@ha
; CHECK-NEXT: fadd 1, 30, 31 ; CHECK-NEXT: fadd 2, 30, 31
; CHECK-NEXT: mtfsf 1, 0 ; CHECK-NEXT: mtfsf 1, 0
; CHECK-NEXT: lfs 0, .LCPI0_1@l(3) ; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
; CHECK-NEXT: fctiwz 1, 1 ; CHECK-NEXT: fctiwz 2, 2
; CHECK-NEXT: stfd 1, 88(1) ; CHECK-NEXT: stfd 2, 88(1)
; CHECK-NEXT: fcmpu 0, 30, 2 ; CHECK-NEXT: fcmpu 0, 30, 1
; CHECK-NEXT: lwz 3, 100(1) ; CHECK-NEXT: lwz 3, 100(1)
; CHECK-NEXT: fcmpu 1, 31, 0 ; CHECK-NEXT: fcmpu 1, 31, 0
; CHECK-NEXT: lwz 4, 92(1) ; CHECK-NEXT: lwz 4, 92(1)
; CHECK-NEXT: crandc 20, 6, 0 ; CHECK-NEXT: crandc 20, 6, 0
; CHECK-NEXT: cror 20, 5, 20 ; CHECK-NEXT: cror 20, 5, 20
; CHECK-NEXT: addis 3, 3, -32768 ; CHECK-NEXT: addis 3, 3, -32768
; CHECK-NEXT: bc 12, 20, .LBB0_15 ; CHECK-NEXT: bc 12, 20, .LBB0_15
; CHECK-NEXT: b .LBB0_16 ; CHECK-NEXT: b .LBB0_16
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines