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Differential D106080

[GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern
ClosedPublic

Authored by paquette on Jul 15 2021, 9:58 AM.

Details

Reviewers
aemerson
Commits
rG5da0f9ab612d: [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern
Summary

It didn't update the opcode while walking through G_INTTOPTR/G_PTRTOINT.

Diff Detail

Event Timeline

paquette created this revision.Jul 15 2021, 9:58 AM
Herald added subscribers: hiraditya, arichardson, rovka. · View Herald TranscriptJul 15 2021, 9:58 AM
paquette requested review of this revision.Jul 15 2021, 9:58 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 15 2021, 9:58 AM
aemerson accepted this revision.Jul 15 2021, 10:04 AM

LGTM, thanks.

This revision is now accepted and ready to land.Jul 15 2021, 10:04 AM
This revision was landed with ongoing or failed builds.Jul 15 2021, 10:19 AM
Closed by commit rG5da0f9ab612d: [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern (authored by paquette). · Explain Why
This revision was automatically updated to reflect the committed changes.
paquette added a commit: rG5da0f9ab612d: [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern.
Harbormaster completed remote builds in B114282: Diff 359029.Jul 15 2021, 11:54 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
1 line
test/
CodeGen/
AArch64/
GlobalISel/
33 lines

Diff 359038

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 4,140 Lines • ▼ Show 20 Lines for (auto &UseMI : MRI.use_nodbg_instructions(Src1Reg)) {
MachineInstr *ConvUseMI = &UseMI; MachineInstr *ConvUseMI = &UseMI;
unsigned ConvUseOpc = ConvUseMI->getOpcode(); unsigned ConvUseOpc = ConvUseMI->getOpcode();
while (ConvUseOpc == TargetOpcode::G_INTTOPTR || while (ConvUseOpc == TargetOpcode::G_INTTOPTR ||
ConvUseOpc == TargetOpcode::G_PTRTOINT) { ConvUseOpc == TargetOpcode::G_PTRTOINT) {
Register DefReg = ConvUseMI->getOperand(0).getReg(); Register DefReg = ConvUseMI->getOperand(0).getReg();
if (!MRI.hasOneNonDBGUse(DefReg)) if (!MRI.hasOneNonDBGUse(DefReg))
break; break;
ConvUseMI = &*MRI.use_instr_nodbg_begin(DefReg); ConvUseMI = &*MRI.use_instr_nodbg_begin(DefReg);
ConvUseOpc = ConvUseMI->getOpcode();
} }
auto LoadStore = ConvUseOpc == TargetOpcode::G_LOAD || auto LoadStore = ConvUseOpc == TargetOpcode::G_LOAD ||
ConvUseOpc == TargetOpcode::G_STORE; ConvUseOpc == TargetOpcode::G_STORE;
if (!LoadStore) if (!LoadStore)
continue; continue;
// Is x[offset2] already not a legal addressing mode? If so then // Is x[offset2] already not a legal addressing mode? If so then
// reassociating the constants breaks nothing (we test offset2 because // reassociating the constants breaks nothing (we test offset2 because
// that's the one we hope to fold into the load or store). // that's the one we hope to fold into the load or store).
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines bb.1:
%2:_(s64) = G_CONSTANT i64 1 %2:_(s64) = G_CONSTANT i64 1
%3:_(s64) = G_ADD %1, %2 %3:_(s64) = G_ADD %1, %2
%4:_(p0) = G_PTR_ADD %0, %3(s64) %4:_(p0) = G_PTR_ADD %0, %3(s64)
%7:_(s32) = G_LOAD %4(p0) :: (load 1) %7:_(s32) = G_LOAD %4(p0) :: (load 1)
$w0 = COPY %7(s32) $w0 = COPY %7(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
... ...
---
name: walk_through_inttoptr
alignment: 4
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: walk_through_inttoptr
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4777
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK: %ptr_to_int:_(s64) = G_PTRTOINT [[PTR_ADD]](p0)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32))
; CHECK: G_STORE [[C2]](s32), [[PTR_ADD]](p0) :: (store (s32))
; CHECK: G_STORE %ptr_to_int(s64), [[PTR_ADD]](p0) :: (store (s64))
; CHECK: $w0 = COPY [[LOAD]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%2:_(s64) = G_CONSTANT i64 4777
%4:_(s64) = G_CONSTANT i64 6
%9:_(s32) = G_CONSTANT i32 0
%10:_(p0) = G_PTR_ADD %0, %2(s64)
%ptr_to_int:_(s64) = G_PTRTOINT %10
%11:_(p0) = G_PTR_ADD %10, %4(s64)
%7:_(s32) = G_LOAD %11(p0) :: (load 4)
G_STORE %9(s32), %10(p0) :: (store 4) ; other use of %10
G_STORE %ptr_to_int(s64), %10(p0) :: (store 8)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0