[mips] Add support for branch-likely pseudo-instructions

[obucina]

Summary

This work is based on r239905.

http://llvm.org/PR22994

[dsanders]

LGTM with a couple nits and a revised commit message.

This work is based on http://reviews.llvm.org/D8537

Nit: Please reference r239905 rather than D8537 when you commit.

https://dmz-portal.mips.com/bugz/show_bug.cgi?id=699

There's rarely a need to reference the MIPS bugzilla here. http://llvm.org/PR22994 is the LLVM ticket for this.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2799–2803

Nit: Don't use redundant braces.

test/MC/Mips/branch-pseudos.s

190–191

Nit: Unnecessary blank lines

[obucina]

New diff contains fix for error reporting when branch likely instructions are used on mips32r6/mips64r6.

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

[dsanders]

New diff contains fix for error reporting when branch likely instructions are used on mips32r6/mips64r6.

I should have thought of that :-). Could you add test cases for this?

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2383–2385

Nit: You seem to have added some extra indentation since the last version of your patch. It was correct in the previous patch

lib/Target/Mips/MipsInstrInfo.td

1698

PredicateControl belongs on MipsAsmPseudoInst rather than CondBranchPseudo

[dsanders]

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

Hmm... I see the problem. We use a custom parser function (parseJumpTarget()) for jump targets for various reasons. However, it never calls parseJumpTarget() for these branch likely instructions on 32r6/64r6 because the the AvailableFeatures leave no possibility of a valid match. Then, because it didn't call parseJumpTarget() it isn't able to parse the remainder of the instruction and (correctly) rejects the instruction but for the wrong reason.

Fixing this properly is going to be a bit big for this patch. We either need to eliminate custom parser functions as far as possible in favour of a generic parser along the lines of your change, or change the handling of custom parsers such that the parsing happens regardless of the prospects for a successful match. For this patch, I'd suggest omitting the fix for the wrong-error issue.

[obucina]

New diff includes formatting fixes, test cases for error on using BL instructions on r6, and a fix for other test cases in test files test/MC/Mips/mips??r6/invalid.s, which were not executing.

[obucina]

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

[obucina]

New diff contain changes that are needed to apply patch to latest version of source code.

[dsanders]

In D10537#191677, @dsanders wrote:

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

Hmm... I see the problem. We use a custom parser function (parseJumpTarget()) for jump targets for various reasons. However, it never calls parseJumpTarget() for these branch likely instructions on 32r6/64r6 because the the AvailableFeatures leave no possibility of a valid match. Then, because it didn't call parseJumpTarget() it isn't able to parse the remainder of the instruction and (correctly) rejects the instruction but for the wrong reason.

Fixing this properly is going to be a bit big for this patch. We either need to eliminate custom parser functions as far as possible in favour of a generic parser along the lines of your change, or change the handling of custom parsers such that the parsing happens regardless of the prospects for a successful match. For this patch, I'd suggest omitting the fix for the wrong-error issue.

Hi,

I believe you already have a conditional LGTM for this patch (for diff 28228) and that the quoted text above contains the only remaining issue. It was asking that you remove the AsmToken::Identifier code (because it introduces another way to parse labels which is already handled elsewhere) and fix the wrong-error issue it was intended to fix in a later patch that deals with other cases too.

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

I'm not sure why this change was made but it seems to have been reverted in the next diff. I'm not sure if that was intended so I thought I should mention it.

New diff contain changes that are needed to apply patch to latest version of source code.

This update removed all the context lines so I can't tell what it did.

[obucina]

Hi,

I believe you already have a conditional LGTM for this patch (for diff 28228) and that the quoted text above contains the only remaining issue. It was asking that you remove the AsmToken::Identifier code (because it introduces another way to parse labels which is already handled elsewhere) and fix the wrong-error issue it was intended to fix in a later patch that deals with other cases too.

OK, I will do this, but now there is another problem to be solved. As You noticed...

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

I'm not sure why this change was made but it seems to have been reverted in the next diff. I'm not sure if that was intended so I thought I should mention it.

There is a problem with ULHU/ULW tests, similar to the one with parsing labels. When PredicateControl is attached to the MipsAsmPseudoInst, second parameter of ULHU/ULW cant be parsed correctly, causing tests to fail. Moving it to CondBranchPseudo is workaround to make the patch applicable.

Please take a look at https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2190

I agree this is not the smartest way to fix it and we have internal communication about possible ways to resolve this.

At the time of creating these diffs, ULHU/ULW support was not implemented, it was added few days after first patch here. This is why this error emerged in later versions. The same problem prevents another patch to be committed, the one for ROL/DROL support, since it also requires PredicateControl attached to MipsAsmPseudoInst.

[dsanders]

There is a problem with ULHU/ULW tests, similar to the one with parsing labels. When PredicateControl is attached to the MipsAsmPseudoInst, second parameter of ULHU/ULW cant be parsed correctly, causing tests to fail. Moving it to CondBranchPseudo is workaround to make the patch applicable.

The problem seems to be that we matched these instructions regardless of the predicates because PredicateControl wasn't in the hierarchy. This is definitely a bug, but it also had a somewhat desirable effect. The expansion emits a better error message than the tablegen-erated code does.

Given that this is a macro, one possible fix would be to drop the ISA_MIPS1_NOT_32R6_64R6 and comment on why it matches for unsupported cases (to emit a more precise error message during the expansion). I'd go with that and try to make the tablegen-erated errors better in a later patch (and remove this hack when that's done).

[obucina]

OK. I agree this is a good way to go. Then, the final corrections for this patch would be to remove AsmToken::Identifier case, remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW, and change tests appropriately.

[dsanders]

remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW

... and comment on why it was removed :-).

... remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW, and change tests appropriately.

I don't think we need to do the latter if we do the former. The former is restoring the 'match but reject bad cases later' behaviour from before this patch which gives us the error messages that are already in the test.

[obucina]

The problem expands, because now another instruction prevents adding PredicateControl to MIspAsmPseudoInst.

class MicroMipsR6Inst16 : PredicateControl {

string DecoderNamespace = "MicroMipsR6";
let InsnPredicates = [HasMicroMips32r6];

}

Workaround is to change

def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                  !strconcat("b", "\t$offset")>,
PredicateControl;

}

into

def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                                    !strconcat("b", "\t$offset")> {
string DecoderNamespace = "MicroMipsR6";

}

Is this good enough?

[obucina]

My bad, its:

def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                  !strconcat("b", "\t$offset")>,
MicroMipsR6Inst16;

[obucina]

The same problem appeared with latest changes from http://reviews.llvm.org/D11675

All these have predicates, but not PredicateControl in hierarchy. Patch is not aplicable until this is fixed.

def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;

def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;

def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6;

def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6;

[obucina]

New diff contains changes necessary to make patch applicable. Predicates are removed from few pseudo instructions in order to enable including PredicateControl into MipsAsmPseudoInst inheritance hierarchy. Some tests are disabled.

[zoran.jovanovic]

LGTM with a nit.

lib/Target/Mips/MipsInstrInfo.td

1747

Please add "FIXME:" at the beginning of the comment.

test/MC/Mips/mips32r6/invalid.s

20

Please add "FIXME:" at the beginning of the comment.

[obucina]

Nit corrections

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::BLT:
   case Mips::BLE:
   case Mips::BGE:
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
+  case Mips::BLTL:
+  case Mips::BLEL:
+  case Mips::BGEL:
+  case Mips::BGTL:
+  case Mips::BLTUL:
+  case Mips::BLEUL:
+  case Mips::BGEUL:
+  case Mips::BGTUL:
   case Mips::SDivMacro:
   case Mips::UDivMacro:
   case Mips::DSDivMacro:
   case Mips::DUDivMacro:
   case Mips::Ulhu:
   case Mips::Ulw:
     return true;
   default:
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::BLT:
   case Mips::BLE:
   case Mips::BGE:
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
   case Mips::BGTU:
+  case Mips::BLTL:
+  case Mips::BLEL:
+  case Mips::BGEL:
+  case Mips::BGTL:
+  case Mips::BLTUL:
+  case Mips::BLEUL:
+  case Mips::BGEUL:
+  case Mips::BGTUL:
     return expandCondBranches(Inst, IDLoc, Instructions);
   case Mips::SDivMacro:
     return expandDiv(Inst, IDLoc, Instructions, false, true);
   case Mips::DSDivMacro:
     return expandDiv(Inst, IDLoc, Instructions, true, true);
   case Mips::UDivMacro:
     return expandDiv(Inst, IDLoc, Instructions, false, false);
   case Mips::DUDivMacro:

 }
 
 bool MipsAsmParser::expandUncondBranchMMPseudo(
     MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
   assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
          "unexpected number of operands");
 
   MCOperand Offset = Inst.getOperand(0);
   if (Offset.isExpr()) {
     Inst.clear();
     Inst.setOpcode(Mips::BEQ_MM);
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
     Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
   } else {
     assert(Offset.isImm() && "expected immediate operand kind");
     if (isIntN(11, Offset.getImm())) {
       // If offset fits into 11 bits then this instruction becomes microMIPS
       // 16-bit unconditional branch instruction.

 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
                                        SmallVectorImpl<MCInst> &Instructions) {
   unsigned PseudoOpcode = Inst.getOpcode();
   unsigned SrcReg = Inst.getOperand(0).getReg();
   unsigned TrgReg = Inst.getOperand(1).getReg();
   const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
 
   unsigned ZeroSrcOpcode, ZeroTrgOpcode;
-  bool ReverseOrderSLT, IsUnsigned, AcceptsEquality;
+  bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
 
   switch (PseudoOpcode) {
   case Mips::BLT:
   case Mips::BLTU:
+  case Mips::BLTL:
+  case Mips::BLTUL:
     AcceptsEquality = false;
     ReverseOrderSLT = false;
-    IsUnsigned = (PseudoOpcode == Mips::BLTU);
+    IsUnsigned = ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
+    IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
     ZeroSrcOpcode = Mips::BGTZ;
     ZeroTrgOpcode = Mips::BLTZ;
     break;
   case Mips::BLE:
   case Mips::BLEU:
+  case Mips::BLEL:
+  case Mips::BLEUL:
     AcceptsEquality = true;
     ReverseOrderSLT = true;
-    IsUnsigned = (PseudoOpcode == Mips::BLEU);
+    IsUnsigned = ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
+    IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
     ZeroSrcOpcode = Mips::BGEZ;
     ZeroTrgOpcode = Mips::BLEZ;
     break;
   case Mips::BGE:
   case Mips::BGEU:
+  case Mips::BGEL:
+  case Mips::BGEUL:
     AcceptsEquality = true;
     ReverseOrderSLT = false;
-    IsUnsigned = (PseudoOpcode == Mips::BGEU);
+    IsUnsigned = ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
+    IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
     ZeroSrcOpcode = Mips::BLEZ;
     ZeroTrgOpcode = Mips::BGEZ;
     break;
   case Mips::BGT:
   case Mips::BGTU:
+  case Mips::BGTL:
+  case Mips::BGTUL:
     AcceptsEquality = false;
     ReverseOrderSLT = true;
-    IsUnsigned = (PseudoOpcode == Mips::BGTU);
+    IsUnsigned = ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
+    IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
     ZeroSrcOpcode = Mips::BLTZ;
     ZeroTrgOpcode = Mips::BGTZ;
     break;
   default:
     llvm_unreachable("unknown opcode for branch pseudo-instruction");
   }
 
   MCInst BranchInst;
bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
   // instead of SLT.
   MCInst SetInst;
   SetInst.setOpcode(IsUnsigned ? Mips::SLTu : Mips::SLT);
   SetInst.addOperand(MCOperand::createReg(ATRegNum));
   SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? TrgReg : SrcReg));
   SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? SrcReg : TrgReg));
   Instructions.push_back(SetInst);
 
+  if (!IsLikely)
     BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE);
+  else
+    BranchInst.setOpcode(AcceptsEquality ? Mips::BEQL : Mips::BNEL);
   BranchInst.addOperand(MCOperand::createReg(ATRegNum));
   BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
   BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
   Instructions.push_back(BranchInst);
   return false;
 }
 
 bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions,

lib/Target/Mips/MicroMips32r6InstrInfo.td

 //
 // MicroMips instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
-                                      !strconcat("b", "\t$offset")>,
-                    MicroMipsR6Inst16;
+                                      !strconcat("b", "\t$offset")> {
+  string DecoderNamespace = "MicroMipsR6";
+}

lib/Target/Mips/MipsInstrFormats.td

class PseudoSE<dag outs, dag ins, list<dag> pattern,
   MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
   let EncodingPredicates = [HasStdEnc];
 }
 
 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
 // These are aliases that require C++ handling to convert to the target
 // instruction, while InstAliases can be handled directly by tblgen.
 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
-  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
+  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
   let isPseudo = 1;
   let Pattern = [];
 }
 //===----------------------------------------------------------------------===//
 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
 //===----------------------------------------------------------------------===//
 
 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,

lib/Target/Mips/MipsInstrInfo.td

def : MipsInstAlias<"sync",
                     (SYNC 0), 1>, ISA_MIPS2;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
 
 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
                            RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
                      !strconcat(instr_asm, "\t$rt, $addr")> ;
 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
 
 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :

 def BLT : CondBranchPseudo<"blt">;
 def BLE : CondBranchPseudo<"ble">;
 def BGE : CondBranchPseudo<"bge">;
 def BGT : CondBranchPseudo<"bgt">;
 def BLTU : CondBranchPseudo<"bltu">;
 def BLEU : CondBranchPseudo<"bleu">;
 def BGEU : CondBranchPseudo<"bgeu">;
 def BGTU : CondBranchPseudo<"bgtu">;
+def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
+def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
+def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
+def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
+
+// Predicates are removed because instructions are matched regardless of
+// predicates, because PredicateControl was not in the hierarchy. This was
+// done to emit more precise error message from expansion function.
+// Once the tablegen-erated errors are made better, this needs to be fixed and
+// predicates needs to be restored.
 
 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
+                                  "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                  "divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
+                                  "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                   "ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
+                                   "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
 
 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
-                                   "ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
+                                   "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
 
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
-                             "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+                             "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
-                            "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+                            "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;

test/MC/Mips/branch-pseudos-bad.s

# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
   bge $7, $8, local_label
 # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
   bgeu $7, $8, local_label
 # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
   bgt $7, $8, local_label
 # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
   bgtu $7, $8, local_label
 # CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+
+  bltl $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bltul $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  blel $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bleul $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgel $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgeul $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgtl $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgtul $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available

test/MC/Mips/branch-pseudos.s

 # CHECK:                       #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
 # CHECK: nop
   bgtu $0, $8, local_label
 # CHECK: nop
   bgtu $0, $0, local_label
 # CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A]
 # CHECK:                         #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
 # CHECK: nop
+
+  bltl $7,$8,local_label
+# CHECK: slt $1, $7, $8                 # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: bnel $1, $zero, local_label    # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltl $7,$8,global_label
+# CHECK: slt $1, $7, $8                 # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: bnel $1, $zero, global_label   # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltl $7,$0,local_label
+# CHECK: bltz $7, local_label           # encoding: [0x04,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltl $0,$8,local_label
+# CHECK: bgtz $8, local_label           # encoding: [0x1d,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltl $0,$0,local_label
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  blel $7,$8,local_label
+# CHECK: slt $1, $8, $7                 # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: beql $1, $zero, local_label    # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  blel $7,$8,global_label
+# CHECK: slt $1, $8, $7                 # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: beql $1, $zero, global_label   # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  blel $7,$0,local_label
+# CHECK: blez $7, local_label           # encoding: [0x18,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  blel $0,$8,local_label
+# CHECK: bgez $8, local_label           # encoding: [0x05,0x01,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  blel $0,$0,local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b local_label                  # encoding: [0x10,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bgel $7,$8,local_label
+# CHECK: slt $1, $7, $8                 # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: beql $1, $zero, local_label    # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgel $7,$8,global_label
+# CHECK: slt $1, $7, $8                 # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: beql $1, $zero, global_label   # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgel $7,$0,local_label
+# CHECK: bgez $7, local_label           # encoding: [0x04,0xe1,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgel $0,$8,local_label
+# CHECK: blez $8, local_label           # encoding: [0x19,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgel $0,$0,local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b local_label                  # encoding: [0x10,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bgtl $7,$8,local_label
+# CHECK: slt $1, $8, $7                 # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: bnel $1, $zero, local_label    # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtl $7,$8,global_label
+# CHECK: slt $1, $8, $7                 # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: bnel $1, $zero, global_label   # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtl $7,$0,local_label
+# CHECK: bgtz $7, local_label           # encoding: [0x1c,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtl $0,$8,local_label
+# CHECK: bltz $8, local_label           # encoding: [0x05,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtl $0,$0,local_label
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bltul $7,$8,local_label
+# CHECK: sltu $1, $7, $8                # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: bnel $1, $zero, local_label    # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltul $7,$8,global_label
+# CHECK: sltu $1, $7, $8                # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: bnel $1, $zero, global_label   # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltul $7,$0,local_label
+# CHECK: bnez $7, local_label           # encoding: [0x14,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltul $0,$8,local_label
+# CHECK: bnez $8, local_label           # encoding: [0x15,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bltul $0,$0,local_label
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bleul $7,$8,local_label
+# CHECK: sltu $1, $8, $7                # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: beql $1, $zero, local_label    # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bleul $7,$8,global_label
+# CHECK: sltu $1, $8, $7                # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: beql $1, $zero, global_label   # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bleul $7,$0,local_label
+# CHECK: beqz $7, local_label           # encoding: [0x10,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bleul $0,$8,local_label
+# CHECK: beqz $8, local_label           # encoding: [0x11,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bleul $0,$0,local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b local_label                  # encoding: [0x10,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bgeul $7,$8,local_label
+# CHECK: sltu $1, $7, $8                # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: beql $1, $zero, local_label    # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgeul $7,$8,global_label
+# CHECK: sltu $1, $7, $8                # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: beql $1, $zero, global_label   # encoding: [0x50,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgeul $7,$0,local_label
+# CHECK: beqz $7, local_label           # encoding: [0x10,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgeul $0,$8,local_label
+# CHECK: beqz $8, local_label           # encoding: [0x11,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgeul $0,$0,local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b local_label                  # encoding: [0x10,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+
+  bgtul $7,$8,local_label
+# CHECK: sltu $1, $8, $7                # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: bnel $1, $zero, local_label    # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtul $7,$8,global_label
+# CHECK: sltu $1, $8, $7                # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: bnel $1, $zero, global_label   # encoding: [0x54,0x20,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: global_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtul $7,$0,local_label
+# CHECK: bnez $7, local_label           # encoding: [0x14,0xe0,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtul $0,$8,local_label
+# CHECK: bnez $8, local_label           # encoding: [0x15,0x00,A,A]
+# CHECK:                                #   fixup A - offset: 0, value: local_label-4, kind: fixup_Mips_PC16
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]
+  bgtul $0,$0,local_label
+# CHECK: nop                            # encoding: [0x00,0x00,0x00,0x00]

test/MC/Mips/mips32r6/invalid.s

 # Instructions that are available for the current ISA but should be rejected by
 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
 
 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
-# RUN: FileCheck %s < %t1 -check-prefix=ASM
+# RUN: FileCheck %s < %t1
 
         .text
+local_label:
         .set noreorder
         .set noat
-        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
-        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
-        ldc2    $8,-21181($at)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sdc2    $20,23157($s2)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        swc2    $25,24880($s0)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
+        ldc2    $8,-21181($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        sdc2    $20,23157($s2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        swc2    $25,24880($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break 1024        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 5     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 7, 1024     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 1024  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        // Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
+        bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        blel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bleul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgeul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgtl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgtul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips64r6/invalid.s

 # Instructions that are available for the current ISA but should be rejected by
 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
 
 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
-# RUN: FileCheck %s < %t1 -check-prefix=ASM
+# RUN: FileCheck %s < %t1
 
         .text
+local_label:
         .set noreorder
   .set noat
-        jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
-        jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
-        ldc2    $8,-21181($at)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
+        jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
+        ldc2    $8,-21181($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break 1024        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 5     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 7, 1024     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 1024  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        // These tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
+        bltl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bltul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        blel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bleul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgel  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgeul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgtl  $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        bgtul $7, $8, local_label  # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled