This is an archive of the discontinued LLVM Phabricator instance.

[mips] Add support for branch-likely pseudo-instructions
ClosedPublic

Authored by obucina on Jun 18 2015, 7:21 AM.

Diff Detail

Event Timeline

obucina updated this revision to Diff 27931.Jun 18 2015, 7:21 AM
obucina retitled this revision from to Add support for branch-likely pseudo-instructions.
obucina updated this object.
obucina edited the test plan for this revision. (Show Details)
obucina added reviewers: zoran.jovanovic, dsanders.
obucina added a subscriber: Unknown Object (MLST).
obucina retitled this revision from Add support for branch-likely pseudo-instructions to [mips] Add support for branch-likely pseudo-instructions.Jun 18 2015, 7:45 AM
dsanders accepted this revision.Jun 18 2015, 8:56 AM
dsanders edited edge metadata.

LGTM with a couple nits and a revised commit message.

This work is based on http://reviews.llvm.org/D8537

Nit: Please reference r239905 rather than D8537 when you commit.

https://dmz-portal.mips.com/bugz/show_bug.cgi?id=699

There's rarely a need to reference the MIPS bugzilla here. http://llvm.org/PR22994 is the LLVM ticket for this.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp
2472–2476

Nit: Don't use redundant braces.

test/MC/Mips/branch-pseudos.s
190–191

Nit: Unnecessary blank lines

This revision is now accepted and ready to land.Jun 18 2015, 8:56 AM
obucina updated this revision to Diff 28019.Jun 19 2015, 7:23 AM
obucina edited edge metadata.

New diff contains fix for error reporting when branch likely instructions are used on mips32r6/mips64r6.

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

New diff contains fix for error reporting when branch likely instructions are used on mips32r6/mips64r6.

I should have thought of that :-). Could you add test cases for this?

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp
2383–2385

Nit: You seem to have added some extra indentation since the last version of your patch. It was correct in the previous patch

lib/Target/Mips/MipsInstrInfo.td
1698

PredicateControl belongs on MipsAsmPseudoInst rather than CondBranchPseudo

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

Hmm... I see the problem. We use a custom parser function (parseJumpTarget()) for jump targets for various reasons. However, it never calls parseJumpTarget() for these branch likely instructions on 32r6/64r6 because the the AvailableFeatures leave no possibility of a valid match. Then, because it didn't call parseJumpTarget() it isn't able to parse the remainder of the instruction and (correctly) rejects the instruction but for the wrong reason.

Fixing this properly is going to be a bit big for this patch. We either need to eliminate custom parser functions as far as possible in favour of a generic parser along the lines of your change, or change the handling of custom parsers such that the parsing happens regardless of the prospects for a successful match. For this patch, I'd suggest omitting the fix for the wrong-error issue.

obucina updated this revision to Diff 28228.Jun 23 2015, 5:55 AM

New diff includes formatting fixes, test cases for error on using BL instructions on r6, and a fix for other test cases in test files test/MC/Mips/mips??r6/invalid.s, which were not executing.

obucina updated this object.Jun 23 2015, 5:59 AM
obucina updated this revision to Diff 28330.Jun 24 2015, 4:12 AM

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

obucina updated this revision to Diff 34027.Sep 4 2015, 6:24 AM

New diff contain changes that are needed to apply patch to latest version of source code.

Please, take a look at AsmToken::Identifier case, since I am not sure this is the right way to parse a label.

You shouldn't need any of the code you added for this. We can already parse labels so specifying 'brtarget' should be sufficient. I'll take a quick look.

Hmm... I see the problem. We use a custom parser function (parseJumpTarget()) for jump targets for various reasons. However, it never calls parseJumpTarget() for these branch likely instructions on 32r6/64r6 because the the AvailableFeatures leave no possibility of a valid match. Then, because it didn't call parseJumpTarget() it isn't able to parse the remainder of the instruction and (correctly) rejects the instruction but for the wrong reason.

Fixing this properly is going to be a bit big for this patch. We either need to eliminate custom parser functions as far as possible in favour of a generic parser along the lines of your change, or change the handling of custom parsers such that the parsing happens regardless of the prospects for a successful match. For this patch, I'd suggest omitting the fix for the wrong-error issue.

Hi,

I believe you already have a conditional LGTM for this patch (for diff 28228) and that the quoted text above contains the only remaining issue. It was asking that you remove the AsmToken::Identifier code (because it introduces another way to parse labels which is already handled elsewhere) and fix the wrong-error issue it was intended to fix in a later patch that deals with other cases too.

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

I'm not sure why this change was made but it seems to have been reverted in the next diff. I'm not sure if that was intended so I thought I should mention it.

New diff contain changes that are needed to apply patch to latest version of source code.

This update removed all the context lines so I can't tell what it did.

Hi,

I believe you already have a conditional LGTM for this patch (for diff 28228) and that the quoted text above contains the only remaining issue. It was asking that you remove the AsmToken::Identifier code (because it introduces another way to parse labels which is already handled elsewhere) and fix the wrong-error issue it was intended to fix in a later patch that deals with other cases too.

OK, I will do this, but now there is another problem to be solved. As You noticed...

PredicateControl moved from CondBranchPseudo to the MipsAsmPseudoInst

I'm not sure why this change was made but it seems to have been reverted in the next diff. I'm not sure if that was intended so I thought I should mention it.

There is a problem with ULHU/ULW tests, similar to the one with parsing labels. When PredicateControl is attached to the MipsAsmPseudoInst, second parameter of ULHU/ULW cant be parsed correctly, causing tests to fail. Moving it to CondBranchPseudo is workaround to make the patch applicable.

Please take a look at https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2190

I agree this is not the smartest way to fix it and we have internal communication about possible ways to resolve this.

At the time of creating these diffs, ULHU/ULW support was not implemented, it was added few days after first patch here. This is why this error emerged in later versions. The same problem prevents another patch to be committed, the one for ROL/DROL support, since it also requires PredicateControl attached to MipsAsmPseudoInst.

There is a problem with ULHU/ULW tests, similar to the one with parsing labels. When PredicateControl is attached to the MipsAsmPseudoInst, second parameter of ULHU/ULW cant be parsed correctly, causing tests to fail. Moving it to CondBranchPseudo is workaround to make the patch applicable.

The problem seems to be that we matched these instructions regardless of the predicates because PredicateControl wasn't in the hierarchy. This is definitely a bug, but it also had a somewhat desirable effect. The expansion emits a better error message than the tablegen-erated code does.

Given that this is a macro, one possible fix would be to drop the ISA_MIPS1_NOT_32R6_64R6 and comment on why it matches for unsupported cases (to emit a more precise error message during the expansion). I'd go with that and try to make the tablegen-erated errors better in a later patch (and remove this hack when that's done).

OK. I agree this is a good way to go. Then, the final corrections for this patch would be to remove AsmToken::Identifier case, remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW, and change tests appropriately.

remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW

... and comment on why it was removed :-).

... remove ISA_MIPS1_NOT_32R6_64R6 from ULHU/ULW, and change tests appropriately.

I don't think we need to do the latter if we do the former. The former is restoring the 'match but reject bad cases later' behaviour from before this patch which gives us the error messages that are already in the test.

The problem expands, because now another instruction prevents adding PredicateControl to MIspAsmPseudoInst.

class MicroMipsR6Inst16 : PredicateControl {

string DecoderNamespace = "MicroMipsR6";
let InsnPredicates = [HasMicroMips32r6];

}

Workaround is to change

def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                  !strconcat("b", "\t$offset")>,
PredicateControl;

}

into

def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                                    !strconcat("b", "\t$offset")> {
string DecoderNamespace = "MicroMipsR6";

}

Is this good enough?

My bad, its:

def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),

                  !strconcat("b", "\t$offset")>,
MicroMipsR6Inst16;

The same problem appeared with latest changes from http://reviews.llvm.org/D11675

All these have predicates, but not PredicateControl in hierarchy. Patch is not aplicable until this is fixed.

def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;

def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;

def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6;

def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),

"ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
obucina updated this revision to Diff 34567.Sep 11 2015, 11:47 AM

New diff contains changes necessary to make patch applicable. Predicates are removed from few pseudo instructions in order to enable including PredicateControl into MipsAsmPseudoInst inheritance hierarchy. Some tests are disabled.

zoran.jovanovic accepted this revision.Sep 14 2015, 8:10 AM
zoran.jovanovic edited edge metadata.

LGTM with a nit.

lib/Target/Mips/MipsInstrInfo.td
1718

Please add "FIXME:" at the beginning of the comment.

test/MC/Mips/mips32r6/invalid.s
20 ↗(On Diff #34567)

Please add "FIXME:" at the beginning of the comment.

obucina updated this revision to Diff 34701.Sep 14 2015, 10:39 AM
obucina edited edge metadata.

Nit corrections

obucina marked 2 inline comments as done.Sep 14 2015, 10:39 AM
This revision was automatically updated to reflect the committed changes.