[mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.

[tomatabacu]

Summary

This does not include support for the immediate variants of these pseudo-instructions.
Fixes llvm.org/PR20968.

[dsanders]

I think there's a couple bugs in this. GAS and IAS behave differently for the following input:

t1:
blt $0, $0, t1
blt $0, $2, t1
blt $2, $0, t1
blt $2, $2, t1
blt $2, $3, t1
bltu $0, $0, t1
bltu $0, $2, t1
bltu $2, $0, t1
bltu $2, $2, t1
bltu $2, $3, t1
ble $0, $0, t1
ble $0, $2, t1
ble $2, $0, t1
ble $2, $2, t1
ble $2, $3, t1
bleu $0, $0, t1
bleu $0, $2, t1
bleu $2, $0, t1
bleu $2, $2, t1
bleu $2, $3, t1
bgt $0, $0, t1
bgt $0, $2, t1
bgt $2, $0, t1
bgt $2, $2, t1
bgt $2, $3, t1
bgtu $0, $0, t1
bgtu $0, $2, t1
bgtu $2, $0, t1
bgtu $2, $2, t1
bgtu $2, $3, t1
bge $0, $0, t1
bge $0, $2, t1
bge $2, $0, t1
bge $2, $2, t1
bge $2, $3, t1
bgeu $0, $0, t1
bgeu $0, $2, t1
bgeu $2, $0, t1
bgeu $2, $2, t1
bgeu $2, $3, t1

Assembling with each assembler then dissassembling the output with objdump shows several differences including missing/additional nops, different offsets (mostly caused by the nop differences), and different instructions. There's also a '...' in the disassembly for the IAS case and I'm not sure what that indicates. In each case the IAS is functionally equivalent, and in some cases is arguably better (e.g. 'blez $0, $0, t1' -> 'b t1'). However, we ought to be producing the same opcodes as GAS given the same input.

---

We should have a test that a warning is emitted when '.set noat' is in effect.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

211

We should rename this to avoid ambiguity between conditional branches and compact branches

1602–1612

This should probably be split into a separate patch which you can commit (with the braces nit fixed) without further review.

1605–1607

Nit: Added unnecessary braces.

lib/Target/Mips/MipsInstrInfo.td

1688

We should rename this to avoid ambiguity between conditional branches and compact branches

[tomatabacu]

Made expansions identical with GAS (will report mismatches as bugs in GAS):

blt  $0, $0 now expands to bltz $zero
ble  $0, $0 now expands to blez $zero
bge  $0, $0 now expands to bgez $zero
bgt  $0, $0 now expands to bgtz $zero
bgtu $0, $0 now expands to bnez $zero

Renamed to avoid possible confusion with compact branches.
Added error test for using conditional branch pseudos after .set noat.
Committed suggested change as rL235601.
Rebased on top of new D8480.

[tomatabacu]

Ping.

[tomatabacu]

Rewrote comment about what I thought were buggy expansions in GAS (turns out I was wrong).
Rebased.

[tomatabacu]

Added .set nomacro warning & test case.
Rebased.

[tomatabacu]

Rebased.

[dsanders]

LGTM with a style nit.

One thing that we will need to address soon is that my while earlier test produces the same results for clang+IAS and gcc+GAS but clang+GAS produces completely different output. Presumably there's a clang-driver bug. Still, IAS is doing the right thing so this patch is good.

Also just an interesting observation, GAS only emits three 'branch ... is always true' warnings whereas IAS emits six. It seems GAS doesn't recognise $0 >= $0 and similar as being always true. IAS is doing the right thing here.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2308–2441

Nit: Use early-return.

Rather than:

if (...) {
  ...
} else if (...) {
  ...
} else {
  ...
}
return false;

Use:

if (...) {
  ...
  return false;
}
if (...) {
  ...
  return false;
}
...
return false;

[tomatabacu]

Addressed LGTM style nit.
Updated the ATReg-related code comment, as a result of this refactoring.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
 
   void expandMemInst(MCInst &Inst, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions, bool isLoad,
                      bool isImmOpnd);
 
   bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                SmallVectorImpl<MCInst> &Instructions);
 
   bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
                        SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandCondBranches(MCInst &Inst, SMLoc IDLoc,
+                          SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
   void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
                   SmallVectorImpl<MCInst> &Instructions);
 
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
switch (Inst.getOpcode()) {
           return Error(IDLoc, "expected immediate operand kind");
         int Imm = Opnd.getImm();
         if ((Imm % 4 != 0) || !isIntN(25, Imm))
           return Error(IDLoc, "immediate operand value out of range");
         break;
     }
   }
 
   if (needsExpansion(Inst)) {
     if (expandInstruction(Inst, IDLoc, Instructions))
       return true;
   } else
     Instructions.push_back(Inst);
 
   // If this instruction has a delay slot and .set reorder is active,
   // emit a NOP after it.
   if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
     createNop(hasShortDelaySlot(Inst.getOpcode()), IDLoc, Instructions);
 
   return false;
 }
 
 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
 
   switch (Inst.getOpcode()) {
   case Mips::LoadImm32:
   case Mips::LoadImm64:
   case Mips::LoadAddrImm32:
   case Mips::LoadAddrReg32:
   case Mips::B_MM_Pseudo:
   case Mips::LWM_MM:
   case Mips::SWM_MM:
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
   case Mips::BneImm:
   case Mips::BeqImm:
+  case Mips::BLT:
+  case Mips::BLE:
+  case Mips::BGE:
+  case Mips::BGT:
+  case Mips::BLTU:
+  case Mips::BLEU:
+  case Mips::BGEU:
+  case Mips::BGTU:
     return true;
   default:
     return false;
   }
 }
 
 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
                                       SmallVectorImpl<MCInst> &Instructions) {
bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
   case Mips::LWM_MM:
     return expandLoadStoreMultiple(Inst, IDLoc, Instructions);
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
     return expandJalWithRegs(Inst, IDLoc, Instructions);
   case Mips::BneImm:
   case Mips::BeqImm:
     return expandBranchImm(Inst, IDLoc, Instructions);
+  case Mips::BLT:
+  case Mips::BLE:
+  case Mips::BGE:
+  case Mips::BGT:
+  case Mips::BLTU:
+  case Mips::BLEU:
+  case Mips::BGEU:
+  case Mips::BGTU:
+    return expandCondBranches(Inst, IDLoc, Instructions);
   }
 }
 
 namespace {
 template <unsigned ShiftAmount>
 void createLShiftOri(MCOperand Operand, unsigned RegNo, SMLoc IDLoc,
                      SmallVectorImpl<MCInst> &Instructions) {
   MCInst tmpInst;
if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
     // It can be implemented as SWM16 or LWM16 instruction.
     NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
 
   Inst.setOpcode(NewOpcode);
   Instructions.push_back(Inst);
   return false;
 }
 
+bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
+                                       SmallVectorImpl<MCInst> &Instructions) {
+  unsigned PseudoOpcode = Inst.getOpcode();
+  unsigned SrcReg = Inst.getOperand(0).getReg();
+  unsigned TrgReg = Inst.getOperand(1).getReg();
+  const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
+
+  unsigned ZeroSrcOpcode, ZeroTrgOpcode;
+  bool ReverseOrderSLT, IsUnsigned, AcceptsEquality;
+
+  switch (PseudoOpcode) {
+  case Mips::BLT:
+  case Mips::BLTU:
+    AcceptsEquality = false;
+    ReverseOrderSLT = false;
+    IsUnsigned = (PseudoOpcode == Mips::BLTU);
+    ZeroSrcOpcode = Mips::BGTZ;
+    ZeroTrgOpcode = Mips::BLTZ;
+    break;
+  case Mips::BLE:
+  case Mips::BLEU:
+    AcceptsEquality = true;
+    ReverseOrderSLT = true;
+    IsUnsigned = (PseudoOpcode == Mips::BLEU);
+    ZeroSrcOpcode = Mips::BGEZ;
+    ZeroTrgOpcode = Mips::BLEZ;
+    break;
+  case Mips::BGE:
+  case Mips::BGEU:
+    AcceptsEquality = true;
+    ReverseOrderSLT = false;
+    IsUnsigned = (PseudoOpcode == Mips::BGEU);
+    ZeroSrcOpcode = Mips::BLEZ;
+    ZeroTrgOpcode = Mips::BGEZ;
+    break;
+  case Mips::BGT:
+  case Mips::BGTU:
+    AcceptsEquality = false;
+    ReverseOrderSLT = true;
+    IsUnsigned = (PseudoOpcode == Mips::BGTU);
+    ZeroSrcOpcode = Mips::BLTZ;
+    ZeroTrgOpcode = Mips::BGTZ;
+    break;
+  default:
+    llvm_unreachable("unknown opcode for branch pseudo-instruction");
+  }
+
+  MCInst BranchInst;
+  bool IsTrgRegZero = (TrgReg == Mips::ZERO);
+  bool IsSrcRegZero = (SrcReg == Mips::ZERO);
+  if (IsSrcRegZero && IsTrgRegZero) {
+    // FIXME: All of these Opcode-specific if's are needed for compatibility
+    // with GAS' behaviour. However, they may not generate the most efficient
+    // code in some circumstances.
+    if (PseudoOpcode == Mips::BLT) {
+      BranchInst.setOpcode(Mips::BLTZ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      return false;
+    }
+    if (PseudoOpcode == Mips::BLE) {
+      BranchInst.setOpcode(Mips::BLEZ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      Warning(IDLoc, "branch is always taken");
+      return false;
+    }
+    if (PseudoOpcode == Mips::BGE) {
+      BranchInst.setOpcode(Mips::BGEZ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      Warning(IDLoc, "branch is always taken");
+      return false;
+    }
+    if (PseudoOpcode == Mips::BGT) {
+      BranchInst.setOpcode(Mips::BGTZ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      return false;
+    }
+    if (PseudoOpcode == Mips::BGTU) {
+      BranchInst.setOpcode(Mips::BNE);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      return false;
+    }
+    if (AcceptsEquality) {
+      // If both registers are $0 and the pseudo-branch accepts equality, it
+      // will always be taken, so we emit an unconditional branch.
+      BranchInst.setOpcode(Mips::BEQ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      Warning(IDLoc, "branch is always taken");
+      return false;
+    }
+    // If both registers are $0 and the pseudo-branch does not accept
+    // equality, it will never be taken, so we don't have to emit anything.
+    return false;
+  }
+  if (IsSrcRegZero || IsTrgRegZero) {
+    if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
+        (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
+      // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or
+      // if the $rt is $0 and the pseudo-branch is BLTU (x < 0),
+      // the pseudo-branch will never be taken, so we don't emit anything.
+      // This only applies to unsigned pseudo-branches.
+      return false;
+    }
+    if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
+        (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
+      // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or
+      // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0),
+      // the pseudo-branch will always be taken, so we emit an unconditional
+      // branch.
+      // This only applies to unsigned pseudo-branches.
+      BranchInst.setOpcode(Mips::BEQ);
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      Warning(IDLoc, "branch is always taken");
+      return false;
+    }
+    if (IsUnsigned) {
+      // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or
+      // if the $rt is $0 and the pseudo-branch is BGTU (x > 0),
+      // the pseudo-branch will be taken only when the non-zero register is
+      // different from 0, so we emit a BNEZ.
+      //
+      // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or
+      // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0),
+      // the pseudo-branch will be taken only when the non-zero register is
+      // equal to 0, so we emit a BEQZ.
+      //
+      // Because only BLEU and BGEU branch on equality, we can use the
+      // AcceptsEquality variable to decide when to emit the BEQZ.
+      BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE);
+      BranchInst.addOperand(
+          MCOperand::createReg(IsSrcRegZero ? TrgReg : SrcReg));
+      BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+      BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+      Instructions.push_back(BranchInst);
+      return false;
+    }
+    // If we have a signed pseudo-branch and one of the registers is $0,
+    // we can use an appropriate compare-to-zero branch. We select which one
+    // to use in the switch statement above.
+    BranchInst.setOpcode(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode);
+    BranchInst.addOperand(MCOperand::createReg(IsSrcRegZero ? TrgReg : SrcReg));
+    BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+    Instructions.push_back(BranchInst);
+    return false;
+  }
+
+  // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the
+  // expansions. If it is not available, we return.
+  unsigned ATRegNum = getATReg(IDLoc);
+  if (!ATRegNum)
+    return true;
+
+  warnIfNoMacro(IDLoc);
+
+  // SLT fits well with 2 of our 4 pseudo-branches:
+  //   BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
+  //   BGT, where $rs > $rt, translates into "slt $at, $rt, $rs".
+  // If the result of the SLT is 1, we branch, and if it's 0, we don't.
+  // This is accomplished by using a BNEZ with the result of the SLT.
+  //
+  // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
+  // and BLE with BGT), so we change the BNEZ into a a BEQZ.
+  // Because only BGE and BLE branch on equality, we can use the
+  // AcceptsEquality variable to decide when to emit the BEQZ.
+  // Note that the order of the SLT arguments doesn't change between
+  // opposites.
+  //
+  // The same applies to the unsigned variants, except that SLTu is used
+  // instead of SLT.
+  MCInst SetInst;
+  SetInst.setOpcode(IsUnsigned ? Mips::SLTu : Mips::SLT);
+  SetInst.addOperand(MCOperand::createReg(ATRegNum));
+  SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? TrgReg : SrcReg));
+  SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? SrcReg : TrgReg));
+  Instructions.push_back(SetInst);
+
+  BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE);
+  BranchInst.addOperand(MCOperand::createReg(ATRegNum));
+  BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
+  BranchInst.addOperand(MCOperand::createExpr(OffsetExpr));
+  Instructions.push_back(BranchInst);
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;
   if (hasShortDelaySlot) {
     NopInst.setOpcode(Mips::MOVE16_MM);
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
     NopInst.addOperand(MCOperand::createReg(Mips::ZERO));
   } else {

lib/Target/Mips/MipsInstrInfo.td

 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
 
 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
                       "jal\t$rd, $rs"> ;
 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
                       "jal\t$rs"> ;
 
 let hasDelaySlot = 1 in {
 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
                                (ins imm64:$imm64, brtarget:$offset),
                                "bne\t$rt, $imm64, $offset">;
 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
                                (ins imm64:$imm64, brtarget:$offset),
                                "beq\t$rt, $imm64, $offset">;
+
+class CondBranchPseudo<string instr_asm> :
+  MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
+                                 brtarget:$offset),
+                    !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
 }
 
+def BLT : CondBranchPseudo<"blt">;
+def BLE : CondBranchPseudo<"ble">;
+def BGE : CondBranchPseudo<"bge">;
+def BGT : CondBranchPseudo<"bgt">;
+def BLTU : CondBranchPseudo<"bltu">;
+def BLEU : CondBranchPseudo<"bleu">;
+def BGEU : CondBranchPseudo<"bgeu">;
+def BGTU : CondBranchPseudo<"bgtu">;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // Load/store pattern templates.
 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
   MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
 

test/MC/Mips/branch-pseudos-bad.s

+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s
+
+# Check for errors when using conditional branch pseudos after .set noat.
+  .set noat
+local_label:
+  blt $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bltu $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  ble $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bleu $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bge $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgeu $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgt $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available
+  bgtu $7, $8, local_label
+# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available

test/MC/Mips/branch-pseudos.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=WARNING
+
+  .text
+local_label:
+  blt $7, $8, local_label
+# CHECK: slt  $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: bnez $1, local_label  # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  blt $7, $8, global_label
+# CHECK: slt  $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  blt $7, $0, local_label
+# CHECK: bltz $7, local_label  # encoding: [0x04,0xe0,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  blt $0, $8, local_label
+# CHECK: bgtz $8, local_label  # encoding: [0x1d,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  blt $0, $0, local_label
+# CHECK: bltz $zero, local_label # encoding: [0x04,0x00,A,A]
+# CHECK:                         #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bltu $7, $8, local_label
+# CHECK: sltu $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: bnez $1, local_label  # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bltu $7, $8, global_label
+# CHECK: sltu $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bltu $7, $0, local_label
+# CHECK: nop
+  bltu $0, $8, local_label
+# CHECK: bnez $8, local_label  # encoding: [0x15,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bltu $0, $0, local_label
+# CHECK: nop
+
+  ble $7, $8, local_label
+# CHECK: slt  $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: beqz $1, local_label  # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  ble $7, $8, global_label
+# CHECK: slt  $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  ble $7, $0, local_label
+# CHECK: blez $7, local_label  # encoding: [0x18,0xe0,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  ble $0, $8, local_label
+# CHECK: bgez $8, local_label  # encoding: [0x05,0x01,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  ble $0, $0, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: blez $zero, local_label # encoding: [0x18,0x00,A,A]
+# CHECK:                         #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bleu $7, $8, local_label
+# CHECK: sltu $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: beqz $1, local_label  # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bleu $7, $8, global_label
+# CHECK: sltu $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bleu $7, $0, local_label
+# CHECK: beqz $7, local_label  # encoding: [0x10,0xe0,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bleu $0, $8, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b  local_label        # encoding: [0x10,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bleu $0, $0, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b  local_label        # encoding: [0x10,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bge $7, $8, local_label
+# CHECK: slt  $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: beqz $1, local_label  # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bge $7, $8, global_label
+# CHECK: slt  $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2a]
+# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bge $7, $0, local_label
+# CHECK: bgez $7, local_label  # encoding: [0x04,0xe1,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bge $0, $8, local_label
+# CHECK: blez $8, local_label  # encoding: [0x19,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bge $0, $0, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: bgez $zero, local_label # encoding: [0x04,0x01,A,A]
+# CHECK:                         #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bgeu $7, $8, local_label
+# CHECK: sltu $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: beqz $1, local_label  # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgeu $7, $8, global_label
+# CHECK: sltu $1, $7, $8       # encoding: [0x00,0xe8,0x08,0x2b]
+# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgeu $7, $0, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b  local_label        # encoding: [0x10,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgeu $0, $8, local_label
+# CHECK: beqz $8, local_label  # encoding: [0x11,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgeu $0, $0, local_label
+# WARNING: :[[@LINE-1]]:3: warning: branch is always taken
+# CHECK: b  local_label        # encoding: [0x10,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bgt $7, $8, local_label
+# CHECK: slt  $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: bnez $1, local_label  # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgt $7, $8, global_label
+# CHECK: slt  $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2a]
+# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgt $7, $0, local_label
+# CHECK: bgtz $7, local_label  # encoding: [0x1c,0xe0,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgt $0, $8, local_label
+# CHECK: bltz $8, local_label  # encoding: [0x05,0x00,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgt $0, $0, local_label
+# CHECK: bgtz  $zero, local_label # encoding: [0x1c,0x00,A,A]
+# CHECK:                          #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+
+  bgtu $7, $8, local_label
+# CHECK: sltu $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: bnez $1, local_label  # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgtu $7, $8, global_label
+# CHECK: sltu $1, $8, $7       # encoding: [0x01,0x07,0x08,0x2b]
+# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgtu $7, $0, local_label
+# CHECK: bnez $7, local_label  # encoding: [0x14,0xe0,A,A]
+# CHECK:                       #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop
+  bgtu $0, $8, local_label
+# CHECK: nop
+  bgtu $0, $0, local_label
+# CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A]
+# CHECK:                         #   fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16
+# CHECK: nop

test/MC/Mips/set-nomacro.s

# CHECK-NOT: warning: macro instruction expanded into multiple instructions
   jal $25
   jal $4, $25
 
   bne $2, 0, 1332
   bne $2, 1, 1332
   beq $2, 0, 1332
   beq $2, 1, 1332
 
+  blt $7, $8, local_label
+  blt $7, $0, local_label
+  blt $0, $8, local_label
+  blt $0, $0, local_label
+
+  bltu $7, $8, local_label
+  bltu $7, $0, local_label
+  bltu $0, $8, local_label
+  bltu $0, $0, local_label
+
+  ble $7, $8, local_label
+  ble $7, $0, local_label
+  ble $0, $8, local_label
+  ble $0, $0, local_label
+
+  bleu $7, $8, local_label
+  bleu $7, $0, local_label
+  bleu $0, $8, local_label
+  bleu $0, $0, local_label
+
+  bge $7, $8, local_label
+  bge $7, $0, local_label
+  bge $0, $8, local_label
+  bge $0, $0, local_label
+
+  bgeu $7, $8, local_label
+  bgeu $7, $0, local_label
+  bgeu $0, $8, local_label
+  bgeu $0, $0, local_label
+
+  bgt $7, $8, local_label
+  bgt $7, $0, local_label
+  bgt $0, $8, local_label
+  bgt $0, $0, local_label
+
+  bgtu $7, $8, local_label
+  bgtu $7, $0, local_label
+  bgtu $0, $8, local_label
+  bgtu $0, $0, local_label
+
   add $4, $5, $6
 
   .set noreorder
   .set nomacro
   li  $8, -16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   li  $8, 16
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions

 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   bne $2, 1, 1332
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   beq $2, 0, 1332
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
   beq $2, 1, 1332
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
+  blt $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  blt $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  blt $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  blt $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bltu $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bltu $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bltu $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bltu $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  ble $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ble $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ble $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ble $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bleu $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bleu $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bleu $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bleu $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bge $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bge $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bge $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bge $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bgeu $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgeu $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgeu $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgeu $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bgt $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgt $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgt $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgt $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  bgtu $7, $8, local_label
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgtu $7, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgtu $0, $8, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  bgtu $0, $0, local_label
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
   add $4, $5, $6
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions