[ASan][AMDGPU] Make shadow offset match X86 on Linux

[rksharma]

Summary

We need to match the shadow memory offset with that of the host (X86) on Linux. Setting IsX86 did not work because we can not tell if we are running on Linux from our target triple. This patch explicitly sets the shadow offset with the desired value.

[rksharma]

Closed by commit rG2e194dec6076

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

static ShadowMapping getShadowMapping(Triple &TargetTriple, int LongSize,
   bool IsArmOrThumb = TargetTriple.isARM() || TargetTriple.isThumb();
   bool IsAArch64 = TargetTriple.getArch() == Triple::aarch64;
   bool IsRISCV64 = TargetTriple.getArch() == Triple::riscv64;
   bool IsWindows = TargetTriple.isOSWindows();
   bool IsFuchsia = TargetTriple.isOSFuchsia();
   bool IsEmscripten = TargetTriple.isOSEmscripten();
   bool IsAMDGPU = TargetTriple.isAMDGPU();
 
-  // Asan support for AMDGPU assumes X86 as the host right now.
-  if (IsAMDGPU)
-    IsX86_64 = true;
-
   ShadowMapping Mapping;
 
   Mapping.Scale = kDefaultShadowScale;
   if (ClMappingScale.getNumOccurrences() > 0) {
     Mapping.Scale = ClMappingScale;
   }
 
   if (LongSize == 32) {
if (LongSize == 32) {
     else if (IsIOS)
       Mapping.Offset = kDynamicShadowSentinel;
     else if (IsMacOS && IsAArch64)
       Mapping.Offset = kDynamicShadowSentinel;
     else if (IsAArch64)
       Mapping.Offset = kAArch64_ShadowOffset64;
     else if (IsRISCV64)
       Mapping.Offset = kRISCV64_ShadowOffset64;
+    else if (IsAMDGPU)
+      Mapping.Offset = (kSmallX86_64ShadowOffsetBase &
+                        (kSmallX86_64ShadowOffsetAlignMask << Mapping.Scale));
     else
       Mapping.Offset = kDefaultShadowOffset64;
   }
 
   if (ClForceDynamicShadow) {
     Mapping.Offset = kDynamicShadowSentinel;
   }
 

llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll

 ; RUN: opt < %s -asan -asan-module -enable-new-pm=0 -S | FileCheck %s
 ; RUN: opt < %s -passes='asan-pipeline' -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
 target triple = "amdgcn-amd-amdhsa"
 
 @x = addrspace(4) global [2 x i32] zeroinitializer, align 4
 
 define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
 entry:
 ; CHECK-LABEL: @constant_load
 ; CHECK-NOT: load
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(4)* %a to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   add i64 %{{.*}}, 3
 ; CHECK:   trunc i64 %{{.*}} to i8
 ; CHECK:   icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]

llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll

 ; CHECK:   call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]])
 ; CHECK:   call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]])
 ; CHECK:   or
 ; CHECK:   icmp ne i1 
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   add i64 %{{.*}}, 3
 ; CHECK:   trunc i64 %{{.*}} to i8
 ; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]

 ; CHECK:   call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]])
 ; CHECK:   call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]])
 ; CHECK:   or
 ; CHECK:   icmp ne i1 
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   {{or|add}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   add i64 %{{.*}}, 3
 ; CHECK:   trunc i64 %{{.*}} to i8
 ; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]

llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll

 ; RUN: opt < %s -asan -asan-module -enable-new-pm=0 -S | FileCheck %s
 ; RUN: opt < %s -passes='asan-pipeline' -S | FileCheck %s
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
 target triple = "amdgcn-amd-amdhsa"
 
 define protected amdgpu_kernel void @global_store(i32 addrspace(1)* %p, i32 %i) sanitize_address {
 entry:
 ; CHECK-LABEL: @global_store
 ; CHECK-NOT: store
 ;
 ; CHECK:   %[[STORE_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[STORE_ADDR]], 3
-; CHECK:   or
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   add i64 %{{.*}}, 3
 ; CHECK:   trunc i64 %{{.*}} to i8
 ; CHECK:   icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]

 
 define protected amdgpu_kernel void @global_load(i32 addrspace(1)* %p, i32 %i) sanitize_address {
 entry:
 ; CHECK-LABEL: @global_load
 ; CHECK-NOT: load
 ;
 ; CHECK:   %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64
 ; CHECK:   lshr i64 %[[LOAD_ADDR]], 3
-; CHECK:   {{add|or}}
+; CHECK:   add i64 %{{.*}}, 2147450880
 ; CHECK:   %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
 ; CHECK:   %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]]
 ; CHECK:   icmp ne i8
 ; CHECK:   br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
 ;
 ; CHECK:   add i64 %{{.*}}, 3
 ; CHECK:   trunc i64 %{{.*}} to i8
 ; CHECK:   icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]