[M68k][NFC] Fix indentation in M68kInstrArithmetic.td

[Jim]

Summary

Merely fix indentation

[myhsu]

LGTM Thanks!
Do you have commit access?

[Jim]

In D104434#2825083, @myhsu wrote:

LGTM Thanks!
Do you have commit access?

I have commit access. Thanks.

llvm/lib/Target/M68k/M68kInstrArithmetic.td

 //===----------------------------------------------------------------------===//
 
 let Defs = [CCR] in {
 let Constraints = "$src = $dst" in {
 
 // $reg, $ccr <- $reg op $reg
 class MxBiArOp_RFRR_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD, MxBead REG>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
              MxArithEncoding<MxBead4Bits<CMD>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
                              REG,
                              !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_2"),
                              MxExtEmpty>>;
 
 /// This Op is similar to the one above except it uses reversed opmode, some
 /// commands(e.g. eor) do not support dEA or rEA modes and require EAd for
 /// register only operations.
 /// NOTE when using dd commands it is irrelevant which opmode to use(as it seems)
 /// but some opcodes support address register and some do not which creates this
 /// mess.
 class MxBiArOp_RFRR_EAd<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
              MxArithEncoding<MxBead4Bits<CMD>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EAd"),
                              MxBeadDReg<2>, MxEncEAd_0, MxExtEmpty>>;
 
 // $reg <- $reg op $imm
 class MxBiArOp_RFRI_xEA<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
-              MN#"."#TYPE.Prefix#"\t$opd, $dst",
-              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
-              MxArithEncoding<MxBead4Bits<CMD>,
-                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
-                              MxBeadDReg<0>, MxEncEAi,
-                              !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
 
 // Again, there are two ways to write an immediate to Dn register either dEA
 // opmode or using *I encoding, and again some instrucitons also support address
 // registers some do not.
 class MxBiArOp_RFRI<string MN, SDNode NODE, MxType TYPE, bits<4> CMD>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.IOp:$opd),
-              MN#"i."#TYPE.Prefix#"\t$opd, $dst",
-              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))],
-              MxArithImmEncoding<MxBead4Bits<CMD>, !cast<MxEncSize>("MxEncSize"#TYPE.Size),
                                 !cast<MxEncEA>("MxEncEA"#TYPE.RLet#"_0"), MxExtEmpty,
                                 !cast<MxEncExt>("MxExtI"#TYPE.Size#"_2")>>;
 
 let mayLoad = 1 in
 class MxBiArOp_RFRM<string MN, SDNode NODE, MxType TYPE, MxOperand OPD, ComplexPattern PAT,
                     bits<4> CMD, MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, OPD:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))],
              MxArithEncoding<MxBead4Bits<CMD>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#TYPE.RLet#"EA"),
                              MxBeadDReg<0>, EA, EXT>>;
 
 } // Constraints
 
 let mayLoad = 1, mayStore = 1 in {
 
 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
 // MxAdd to survive the match and subsequent mismatch.
 class MxBiArOp_FMR<string MN, SDNode NODE, MxType TYPE,
                    MxOperand MEMOpd, ComplexPattern MEMPat,
                    bits<4> CMD, MxEncEA EA, MxEncExt EXT>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [],
              MxArithEncoding<MxBead4Bits<CMD>,
                              !cast<MxEncOpMode>("MxOpMode"#TYPE.Size#"EA"#TYPE.RLet),
                              MxBeadDReg<1>, EA, EXT>>;
 
 class MxBiArOp_FMI<string MN, SDNode NODE, MxType TYPE,
                    MxOperand MEMOpd, ComplexPattern MEMPat,
                    bits<4> CMD, MxEncEA MEMEA, MxEncExt MEMExt>
     : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd),
              MN#"."#TYPE.Prefix#"\t$opd, $dst",
              [],
              MxArithImmEncoding<MxBead4Bits<CMD>,
                                 !cast<MxEncSize>("MxEncSize"#TYPE.Size),
                                 MEMEA, MEMExt,
                                 !cast<MxEncExt>("MxExtI"#TYPE.Size#"_1")>>;
 } // mayLoad, mayStore
 } // Defs = [CCR]
 
 multiclass MxBiArOp_DF<string MN, SDNode NODE, bit isComm,
                        bits<4> CMD, bits<4> CMDI> {
 
   // op $mem, $reg
   def NAME#"8dk"  : MxBiArOp_RFRM<MN, NODE, MxType8d,  MxType8.KOp,  MxType8.KPat,

 class MxExtEncoding<MxBead3Bits OPMODE>
     : MxEncoding<MxBeadDReg<0>, MxBead3Bits<0b000>, OPMODE,
                  MxBead3Bits<0b100>, MxBead4Bits<0b0100>>;
 
 let Defs = [CCR] in
 let Constraints = "$src = $dst" in
 class MxExt<MxType TO, MxType FROM>
     : MxInst<(outs TO.ROp:$dst), (ins TO.ROp:$src),
-              "ext."#TO.Prefix#"\t$src", [],
-              MxExtEncoding<!cast<MxBead3Bits>("MxExtOpmode_"#TO.Prefix#FROM.Prefix)>>;
 
 def EXT16 : MxExt<MxType16d, MxType8d>;
 def EXT32 : MxExt<MxType32d, MxType16d>;
 
 def : Pat<(sext_inreg i16:$src, i8),  (EXT16 $src)>;
 def : Pat<(sext_inreg i32:$src, i16), (EXT32 $src)>;
 def : Pat<(sext_inreg i32:$src, i8),
           (EXT32 (MOVXd32d16 (EXT16 (EXTRACT_SUBREG $src, MxSubRegIndex16Lo))))>;
foreach N = ["add", "addc"] in {
   // we make sure it will be selected over LEAp
   let AddedComplexity = 15 in {
   def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd),
             (ADD32ri MxXRD32:$src, imm:$opd)>;
   } // AddedComplexity = 15
 
   // add imm, (An)
   def : Pat<(store (!cast<SDNode>(N) (load MxType8.JPat:$dst), MxType8.IPat:$opd),
-                    MxType8.JPat:$dst),
             (ADD8ji MxType8.JOp:$dst, imm:$opd)>;
   def : Pat<(store (!cast<SDNode>(N) (load MxType16.JPat:$dst), MxType16.IPat:$opd),
-                    MxType16.JPat:$dst),
             (ADD16ji MxType16.JOp:$dst, imm:$opd)>;
   def : Pat<(store (!cast<SDNode>(N) (load MxType32.JPat:$dst), MxType32.IPat:$opd),
-                    MxType32.JPat:$dst),
             (ADD32ji MxType32.JOp:$dst, imm:$opd)>;
 
 } // foreach add, addc
 
 def : Pat<(adde i8 :$src, i8 :$opd), (ADDX8dd  MxDRD8 :$src, MxDRD8 :$opd)>;
 def : Pat<(adde i16:$src, i16:$opd), (ADDX16dd MxDRD16:$src, MxDRD16:$opd)>;
 def : Pat<(adde i32:$src, i32:$opd), (ADDX32dd MxDRD32:$src, MxDRD32:$opd)>;