[compiler-rt] Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

[kristof.beyls]

Summary

The dsb after instruction cache invalidation only needs to be executed
if any instruction cache invalidation did happen.
Without this change, if the CTR_EL0.DIC bit indicates that instruction
cache invalidation is not needed, __clear_cache would execute two dsb
instructions in a row; with the second one being unnecessary.

[danielkiss]

LGTM

compiler-rt/lib/builtins/clear_cache.c

#elif defined(__aarch64__) && !defined(__APPLE__)
 
   // If CTR_EL0.DIC is set, instruction cache invalidation to the point of
   // unification is not required for instruction to data coherence.
   if (((ctr_el0 >> 29) & 0x1) == 0x0) {
     const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
     for (addr = xstart & ~(icache_line_size - 1); addr < xend;
          addr += icache_line_size)
       __asm __volatile("ic ivau, %0" ::"r"(addr));
-  }
     __asm __volatile("dsb ish");
+  }
   __asm __volatile("isb sy");
 #elif defined(__powerpc64__)
   const size_t line_size = 32;
   const size_t len = (uintptr_t)end - (uintptr_t)start;
 
   const uintptr_t mask = ~(line_size - 1);
   const uintptr_t start_line = ((uintptr_t)start) & mask;
   const uintptr_t end_line = ((uintptr_t)start + len + line_size - 1) & mask;