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[mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions
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Authored by zbuljan on Jun 9 2015, 4:53 AM.

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Summary

The patch implements microMIPSr6 CACHEE, WRPGPR and WSBH instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

zbuljan updated this revision to Diff 27372.Jun 9 2015, 4:53 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions.
zbuljan updated this object.
zbuljan edited the test plan for this revision. (Show Details)
zbuljan added reviewers: zoran.jovanovic, dsanders.
zbuljan added subscribers: petarj, Unknown Object (MLST).
dsanders accepted this revision.Sep 14 2015, 5:59 AM
dsanders edited edge metadata.

LGTM with some nits.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp
1109–1117 ↗(On Diff #27372)

Indentation (labels are the same indentation level as the switch in LLVM's style).

lib/Target/Mips/MicroMips32r6InstrFormats.td
47 ↗(On Diff #27372)

As per the other reviews, please assign these to fields named 'base' and 'offset' to make the special encoding self-documenting.

bits<21> addr;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};

...
let Inst{20-16} = base;
...
let Inst{8-0} = offset;
lib/Target/Mips/MicroMips32r6InstrInfo.td
263 ↗(On Diff #27372)

wrpgpr isn't a 'word swap', it's a register move.

264 ↗(On Diff #27372)

'WORDSWAP' is misleading. WSBH swaps bytes within each half-word (1234 -> 2143).

This revision is now accepted and ready to land.Sep 14 2015, 5:59 AM
This revision was automatically updated to reflect the committed changes.