[X86] Fold (shift undef, X)->0 for vector shifts by immediate.

[craig.topper]

Summary

We could previously do this by accident through the later
call to getTargetConstantBitsFromNode I think, but that only worked
if N0 had a single use. This patch makes it explicit for undef and
doesn't have a use count check.

I think this is needed to move the (shl X, 1)->(add X, X)
fold to isel for PR50468. We need to be sure X won't be IMPLICIT_DEF
which might prevent the same vreg from being used for both operands.

[RKSimon]

LGTM

llvm/test/CodeGen/X86/vec_shift5.ll

193

precommit - and maybe include a shift-by-one instruction ?

llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0);
   unsigned NumBitsPerElt = VT.getScalarSizeInBits();
   assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
          "Unexpected value type");
   assert(N->getOperand(1).getValueType() == MVT::i8 &&
          "Unexpected shift amount type");
 
+  // (shift undef, X) -> 0
+  if (N0.isUndef())
+    return DAG.getConstant(0, SDLoc(N), VT);
+
   // Out of range logical bit shifts are guaranteed to be zero.
   // Out of range arithmetic bit shifts splat the sign bit.
   unsigned ShiftVal = N->getConstantOperandVal(1);
   if (ShiftVal >= NumBitsPerElt) {
     if (LogicalShift)
       return DAG.getConstant(0, SDLoc(N), VT);
     ShiftVal = NumBitsPerElt - 1;
   }

llvm/test/CodeGen/X86/vec_shift5.ll

 }
 
 ; Make sure we fold fully undef input vectors. We previously folded only when
 ; undef had a single use so use 2 undefs.
 define <4 x i32> @test17(<4 x i32> %a0, <4 x i32>* %dummy) {
 ; X86-LABEL: test17:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    pslld $6, %xmm0
-; X86-NEXT:    movdqa %xmm0, (%eax)
-; X86-NEXT:    pslld $7, %xmm0
+; X86-NEXT:    xorps %xmm0, %xmm0
+; X86-NEXT:    movaps %xmm0, (%eax)
+; X86-NEXT:    xorps %xmm0, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test17:
 ; X64:       # %bb.0:
-; X64-NEXT:    pslld $6, %xmm0
-; X64-NEXT:    movdqa %xmm0, (%rdi)
-; X64-NEXT:    pslld $7, %xmm0
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    movaps %xmm0, (%rdi)
+; X64-NEXT:    xorps %xmm0, %xmm0
 ; X64-NEXT:    retq
   %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 6)
   store <4 x i32> %a, <4 x i32>* %dummy
   %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 7)
   ret <4 x i32> %res
 }
 
 define <4 x i32> @test18(<4 x i32> %a0, <4 x i32>* %dummy) {
 ; X86-LABEL: test18:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    pslld $3, %xmm0
-; X86-NEXT:    movdqa %xmm0, (%eax)
-; X86-NEXT:    pslld $1, %xmm0
+; X86-NEXT:    xorps %xmm0, %xmm0
+; X86-NEXT:    movaps %xmm0, (%eax)
+; X86-NEXT:    xorps %xmm0, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test18:
 ; X64:       # %bb.0:
-; X64-NEXT:    pslld $3, %xmm0
-; X64-NEXT:    movdqa %xmm0, (%rdi)
-; X64-NEXT:    pslld $1, %xmm0
+; X64-NEXT:    xorps %xmm0, %xmm0
+; X64-NEXT:    movaps %xmm0, (%rdi)
+; X64-NEXT:    xorps %xmm0, %xmm0
 ; X64-NEXT:    retq
   %a = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 3)
   store <4 x i32> %a, <4 x i32>* %dummy
   %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> undef, i32 1)
   ret <4 x i32> %res
 }
 
 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32)
 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32)
 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32)
 declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32)
 declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32)
 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32)
 declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32)