[SystemZ] Return true from preferZeroCompareBranch()

[jonpa]

Summary

Doing this seems to eliminate compares overall on benchmarks:

cijlh          :                78588                77953     -635
ahik           :                72595                71970     -625
jlh            :               165486               166049     +563
ahi            :                89115                89660     +545
je             :               337157               337319     +162
...

[uweigand]

Indeed, this looks like a win. LGTM.

llvm/lib/Target/SystemZ/SystemZISelLowering.h

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
     //
     // (c) there are no multiplication instructions for the widest integer
     //     type (v2i64).
     if (VT.getScalarSizeInBits() % 8 == 0)
       return TypeWidenVector;
     return TargetLoweringBase::getPreferredVectorAction(VT);
   }
   bool isCheapToSpeculateCtlz() const override { return true; }
+  bool preferZeroCompareBranch() const override { return true; }
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
                          EVT) const override;
   bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                   EVT VT) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   bool hasInlineStackProbe(MachineFunction &MF) const override;
   bool isLegalICmpImmediate(int64_t Imm) const override;

llvm/test/CodeGen/SystemZ/codegenprepare-form-OF-ops.ll

 ; CHECK: locgrle %r2, %r0
 ; CHECK: br      %r14
 bb:
   %tmp10 = icmp eq i64 %arg, 0
   %tmp11 = sub nsw i64 %arg, 1
   %tmp12 = select i1 %tmp10, i64 %tmp11, i64 %arg
   ret i64 %tmp12
 }
+
+define i32 @optbranch_32(i32 %Arg) {
+; CHECK-LABEL: optbranch_32:
+; CHECK:        alhsik  %r2, %r2, 1
+; CHECK-NEXT:   bler  %r14
+; CHECK-NEXT:   .LBB4_1:
+; CHECK-NEXT:   lhi %r2, -1
+; CHECK-NEXT:   br  %r14
+bb:
+  %i1 = icmp eq i32 %Arg, -1
+  br i1 %i1, label %bb2, label %bb3
+
+bb2:
+  ret i32 -1
+
+bb3:
+  %i4 = add nuw i32 %Arg, 1
+  ret i32 %i4
+}
+
+define i64 @optbranch_64(i64 %Arg) {
+; CHECK-LABEL: optbranch_64:
+; CHECK:        alghsik %r2, %r2, 1
+; CHECK-NEXT:   bler  %r14
+; CHECK-NEXT:   .LBB5_1:
+; CHECK-NEXT:   lghi  %r2, -1
+; CHECK-NEXT:   br  %r14
+bb:
+  %i1 = icmp eq i64 %Arg, -1
+  br i1 %i1, label %bb2, label %bb3
+
+bb2:
+  ret i64 -1
+
+bb3:
+  %i4 = add nuw i64 %Arg, 1
+  ret i64 %i4
+}