[NFC][scudo] Add paramenters DCHECKs

[cryptoad]

This might trigger sign-compare warnings like https://reviews.llvm.org/D103029?

[vitalybuka]

In D103042#2778030, @cryptoad wrote:

This might trigger sign-compare warnings like https://reviews.llvm.org/D103029?

It does not, as D103029 exposes gtest specific issue.
normally if (0 < uptr_var) ... should not produce the warning.

Scudo check has a different one, and I'll upload a patch.

[pcc]

compiler-rt/lib/scudo/standalone/memtag.h

215

This isn't right. The size is not required to be aligned to 16.

220

I'm not sure if this will always be true. Have you run the tests with MTE enabled?

231

Same as line 220.

[vitalybuka]

compiler-rt/lib/scudo/standalone/memtag.h

215

It's about return value.
This code returns aligned end?

this one passes DCHECK

for (uptr Size = 0; Size < 4 * archMemoryTagGranuleSize(); ++Size) {
    uptr Tagged = addFixedTag(P, 5);
    uptr TaggedEnd = Tagged + Size;

    EXPECT_EQ(roundUpTo(TaggedEnd, archMemoryTagGranuleSize()),
              storeTags(Tagged, TaggedEnd));
}

220

Yes, not all tests pass, with or without the patch, but nothing fails any of this DCHECKs.

QEMU itself crashes on nonaligned address https://github.com/qemu/qemu/blob/master/linux-user/aarch64/cpu_loop.c#L141
Shouldn't stg ptr be aligned?

231

We have few calls there and as I understand the code, they can't be misaligned at current call-sites.

[pcc]

compiler-rt/lib/scudo/standalone/memtag.h

215

Oh, right. This seems okay then.

220

They certainly all pass on Android. Perhaps they aren't passing for you because you're using glibc or qemu user mode or something.

Yes, looking at the ARM ARM the pointer is required to be aligned.

231

Okay then.

compiler-rt/lib/scudo/standalone/memtag.h

__asm__ __volatile__(
       .arch_extension memtag
       irg %[TaggedPtr], %[Ptr], %[ExcludeMask]
       )"
       : [TaggedPtr] "=r"(TaggedPtr)
       : [Ptr] "r"(Ptr), [ExcludeMask] "r"(ExcludeMask));
   return TaggedPtr;
 }
 
-inline uptr addFixedTag(uptr Ptr, uptr Tag) { return Ptr | (Tag << 56); }
+inline uptr addFixedTag(uptr Ptr, uptr Tag) {
+  DCHECK_LT(Tag, 16);
+  return Ptr | (Tag << 56);
+}
 
 inline uptr storeTags(uptr Begin, uptr End) {
-  DCHECK(Begin % 16 == 0);
+  DCHECK_EQ(0, Begin % 16);
   uptr LineSize, Next, Tmp;
   __asm__ __volatile__(
       R"(
     .arch_extension memtag
 
     // Compute the cache line size in bytes (DCZID_EL0 stores it as the log2
     // of the number of 4-byte words) and bail out to the slow path if DCZID_EL0
     // indicates that the DC instructions are unavailable.
3:
     b 3b
 
   4:
   )"
       : [Cur] "+&r"(Begin), [LineSize] "=&r"(LineSize), [Next] "=&r"(Next),
         [Tmp] "=&r"(Tmp)
       : [End] "r"(End)
       : "memory");
+  DCHECK_EQ(0, Begin % 16);
   return Begin;
 }
 
 inline void storeTag(uptr Ptr) {
+  DCHECK_EQ(0, Ptr % 16);
   __asm__ __volatile__(R"(
     .arch_extension memtag
     stg %0, [%0]
   )"
                        :
                        : "r"(Ptr)
                        : "memory");
 }
 
 inline uptr loadTag(uptr Ptr) {
+  DCHECK_EQ(0, Ptr % 16);
   uptr TaggedPtr = Ptr;
   __asm__ __volatile__(
       R"(
       .arch_extension memtag
       ldg %0, [%0]
       )"
       : "+r"(TaggedPtr)
       :