[InstCombine] Fold more select of selects using isImpliedCondition

[aqjune]

Summary

This is a simple folding that does these:

select x_inv, true, (select y, x, false)
=>
select x_inv, true, y

https://alive2.llvm.org/ce/z/-STJ2d

select (select y, x, false), true, x_inv
=>
select y, true, x_inv

https://alive2.llvm.org/ce/z/6ruYt6

[aqjune]

Alive2 link: https://alive2.llvm.org/ce/z/-STJ2d

[spatel]

LGTM - seems like there must be more combinations of these implied condition patterns, so we may want to split it into another function and try to make the matching more systematic/complete.

[nikic]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2776

Shouldn't we also handle select (select a, b, false), true, c -> select a, true, c here? It seems odd to handle 3 out of 4 patterns.

[aqjune]

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

2776

Fine, since this is just a repetition of the current change I included it in this patch.

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

if (match(CondVal, m_Select(m_Value(A), m_One(), m_Value(B))) &&
         return replaceOperand(SI, 0, A);
     }
     if (match(TrueVal, m_Select(m_Value(A), m_One(), m_Value(B))) &&
         match(FalseVal, m_Zero())) {
       Optional<bool> Res = isImpliedCondition(CondVal, B, DL);
       if (Res && *Res == false)
         return replaceOperand(SI, 1, A);
     }
+    // select c, true, (select a, b, false)  -> select c, true, a
+    // select (select a, b, false), true, c  -> select a, true, c
+    //   if c = false implies that b = true
+    if (match(TrueVal, m_One()) &&
+        match(FalseVal, m_Select(m_Value(A), m_Value(B), m_Zero()))) {
+      Optional<bool> Res = isImpliedCondition(CondVal, B, DL, false);
+      if (Res && *Res == true)
+        return replaceOperand(SI, 2, A);
+    }
+    if (match(CondVal, m_Select(m_Value(A), m_Value(B), m_Zero())) &&
+        match(TrueVal, m_One())) {
+      Optional<bool> Res = isImpliedCondition(FalseVal, B, DL, false);
+      if (Res && *Res == true)
+        return replaceOperand(SI, 0, A);
+    }
 
     // sel (sel c, a, false), true, (sel !c, b, false) -> sel c, a, b
     // sel (sel !c, a, false), true, (sel c, b, false) -> sel c, b, a
     Value *C1, *C2;
     if (match(CondVal, m_Select(m_Value(C1), m_Value(A), m_Zero())) &&
         match(TrueVal, m_One()) &&
         match(FalseVal, m_Select(m_Value(C2), m_Value(B), m_Zero()))) {
       if (match(C2, m_Not(m_Specific(C1)))) // first case

llvm/test/Transforms/InstCombine/select-safe-transforms.ll

;
   %and1 = select i1 %c, i1 %a, i1 false
   %and2 = select i1 %not, i1 %b, i1 false
   %or = select i1 %and1, i1 true, i1 %and2
   ret i1 %or
 }
 
 define i1 @orn_and_cmp_1_logical(i37 %a, i37 %b, i1 %y) {
 ; CHECK-LABEL: @orn_and_cmp_1_logical(
-; CHECK-NEXT:    [[X:%.*]] = icmp sgt i37 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i37 [[A]], [[B]]
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y:%.*]], i1 [[X]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[AND]]
+; CHECK-NEXT:    [[X_INV:%.*]] = icmp sle i37 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[X_INV]], i1 true, i1 [[Y:%.*]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp sgt i37 %a, %b
   %x_inv = icmp sle i37 %a, %b
   %and = select i1 %y, i1 %x, i1 false
   %or = select i1 %x_inv, i1 true, i1 %and
   ret i1 %or
 }
 
 define i1 @orn_and_cmp_2_logical(i16 %a, i16 %b, i1 %y) {
 ; CHECK-LABEL: @orn_and_cmp_2_logical(
-; CHECK-NEXT:    [[X:%.*]] = icmp sge i16 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[X_INV:%.*]] = icmp slt i16 [[A]], [[B]]
-; CHECK-NEXT:    [[AND:%.*]] = select i1 [[Y:%.*]], i1 [[X]], i1 false
-; CHECK-NEXT:    [[OR:%.*]] = select i1 [[AND]], i1 true, i1 [[X_INV]]
+; CHECK-NEXT:    [[X_INV:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[Y:%.*]], i1 true, i1 [[X_INV]]
 ; CHECK-NEXT:    ret i1 [[OR]]
 ;
   %x = icmp sge i16 %a, %b
   %x_inv = icmp slt i16 %a, %b
   %and = select i1 %y, i1 %x, i1 false
   %or = select i1 %and, i1 true, i1 %x_inv
   ret i1 %or
 }