[WebAssembly] Mark abs of v2i64 as legal

[tlively]

Summary

We previously had an ISel pattern for i64x2.abs, but because the ISDNode was not
marked legal for v2i64, the instruction was not being selected.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

if (Subtarget->hasSIMD128()) {
     setTargetDAGCombine(ISD::CONCAT_VECTORS);
 
     // Support saturating add for i8x16 and i16x8
     for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
       for (auto T : {MVT::v16i8, MVT::v8i16})
         setOperationAction(Op, T, Legal);
 
     // Support integer abs
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
       setOperationAction(ISD::ABS, T, Legal);
 
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes
     for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                    MVT::v2f64})
       setOperationAction(ISD::BUILD_VECTOR, T, Custom);
 
     // We have custom shuffle lowering to expose the shuffle mask

llvm/test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128-NEXT: .functype mul_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128: i64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: abs_v2i64:
+; NO-SIMD128-NOT: i64x2:
+; SIMD128-NEXT: .functype abs_v2i64 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i64x2.abs $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+define <2 x i64> @abs_v2i64(<2 x i64> %x) {
+  %a = sub <2 x i64> zeroinitializer, %x
+  %b = icmp slt <2 x i64> %x, zeroinitializer
+  %c = select <2 x i1> %b, <2 x i64> %a, <2 x i64> %x
+  ret <2 x i64> %c
+}
+
 ; CHECK-LABEL: neg_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.neg $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @neg_v2i64(<2 x i64> %x) {
   %a = sub <2 x i64> <i64 0, i64 0>, %x
   ret <2 x i64> %a