This is an archive of the discontinued LLVM Phabricator instance.

Differential D101127

AMDGPU: Fix assert on inline asm on gfx90a
ClosedPublic

Authored by arsenm on Apr 22 2021, 7:35 PM.

Details

Reviewers
rampitec
Summary

This was assuming all mayLoad instructions have one def.

Diff Detail

Event Timeline

arsenm created this revision.Apr 22 2021, 7:35 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptApr 22 2021, 7:35 PM
arsenm requested review of this revision.Apr 22 2021, 7:35 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 22 2021, 7:35 PM
Herald added a subscriber: wdng. · View Herald Transcript
rampitec accepted this revision.Apr 22 2021, 8:11 PM
This revision is now accepted and ready to land.Apr 22 2021, 8:11 PM
Harbormaster completed remote builds in B100432: Diff 339848.Apr 22 2021, 9:01 PM
arsenm closed this revision.Apr 23 2021, 6:00 AM

b58332774f85efc1d7b88cd7985a93b63bf8de74

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
2 lines
test/
CodeGen/
AMDGPU/
13 lines
15 lines

Diff 339848

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 1,649 Lines • ▼ Show 20 Linesbool SIFoldOperands::tryFoldLCSSAPhi(MachineInstr &PHI) {
LLVM_DEBUG(dbgs() << "Folded " << PHI); LLVM_DEBUG(dbgs() << "Folded " << PHI);
return true; return true;
} }
// Attempt to convert VGPR load to an AGPR load. // Attempt to convert VGPR load to an AGPR load.
bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) { bool SIFoldOperands::tryFoldLoad(MachineInstr &MI) {
assert(MI.mayLoad()); assert(MI.mayLoad());
if (!ST->hasGFX90AInsts() || !MI.getNumOperands()) if (!ST->hasGFX90AInsts() || MI.getNumExplicitDefs() != 1)
return false; return false;
MachineOperand &Def = MI.getOperand(0); MachineOperand &Def = MI.getOperand(0);
if (!Def.isDef()) if (!Def.isDef())
return false; return false;
Register DefReg = Def.getReg(); Register DefReg = Def.getReg();
▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/swdev282079.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s
define protected amdgpu_kernel void @foo(i64 addrspace(1)* %arg, i64 addrspace(1)* %arg1) {
bb:
%tmp = addrspacecast i64* addrspace(5)* null to i64**
%tmp2 = call i64 @eggs(i64* undef) #1
%tmp3 = load i64*, i64** %tmp, align 8
%tmp4 = getelementptr inbounds i64, i64* %tmp3, i64 undef
store i64 %tmp2, i64* %tmp4, align 8
ret void
}
declare hidden i64 @eggs(i64*)

llvm/test/CodeGen/AMDGPU/swdev282079.mir

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines bb.0:
%0:vgpr_32 = V_MOV_B32_e32 2, implicit $exec %0:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
%1:vgpr_32 = COPY $vgpr0 %1:vgpr_32 = COPY $vgpr0
%2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 %2:vreg_64_align2 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
%3:vreg_64_align2 = IMPLICIT_DEF %3:vreg_64_align2 = IMPLICIT_DEF
FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store 8) FLAT_STORE_DWORDX2 killed %3, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store 8)
S_ENDPGM 0 S_ENDPGM 0
... ...
# This would crash looking for a def in any mayLoad instruction
---
name: fold_inlineasm_def
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: fold_inlineasm_def
; CHECK: INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
; CHECK: S_ENDPGM 0
INLINEASM &"s_waitcnt vmcnt($0)", 41 /* sideeffect mayload isconvergent attdialect */, 13 /* imm */, 0
S_ENDPGM 0
...