[PowerPC] Improve f32 to i32 bitcast code gen

[Conanap]

Summary

The code gen for f32 to i32 bitcast is not currently the most efficient. For example:

int foo(float f) {
  return *(int*)&f;
}

Generates:

xscvdpspn vs0, f1
xxsldwi vs0, vs0, vs0, 3
mffprwz	r3, f0

However, xxsldwi is actually not needed as xscvdpspn already splats the value.

This patch removes that instruction for this specific code gen.

[nemanjai]

This will still produce a redundant XXSLDWI:

vector float test(vector float a, float b) {
  a[3] = b;
  return a;
}

when compiled with -mcpu=pwr9.

[Conanap]

Updated to remove uncessary xrsp and other xxsldwi as well

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2798

These COPY_TO_REGCLASS should probably be SUBREG_TO_REG (all of them by the looks of it).

4218

I am not really seeing the tests for these.
Can we add some tests of the form

vector float test(vector float a, double b) {
  a[1] = b;
  return a;
}

[Conanap]

Updated COPY_TO_REGCLASS to SUBREG_TO_REG, added a test case.

[nemanjai]

Please add the missing BE handling.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2797

Although it is accurate that this specific instruction clears the other bits, all the other uses of SUBREG_TO_REG in the back end use (i64 1) and I don't think it is particularly useful to part with that here.

4218

These also need to be added for big endian subtargets.

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

748

Notice that this still generates the undesired code due to missing the new patterns for big endian subtargets.

[Conanap]

Added big-endian pattern

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
                                  (select i1:$cond, f32:$T, f32:$F))]>;
 }
 }
 
 //----------------------------- DAG Definitions ------------------------------//
 
 // Output dag used to bitcast f32 to i32 and f64 to i64
 def Bitcast {
-  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI (XSCVDPSPN $A),
-                      (XSCVDPSPN $A), 3), sub_64)));
+  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
   dag DblToLong = (i64 (MFVSRD $A));
 }
 
 def FpMinMax {
   dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC),
                                           (COPY_TO_REGCLASS $B, VSFRC)),
                                  VSSRC);
   dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC),
defm : ScalToVecWPermute<
   v4i32, FltToIntLoad.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, FltToUIntLoad.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), sub_64)>;
 def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
           (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
 def : Pat<(v2f64 (PPCldsplat xoaddr:$A)),
           (v2f64 (LXVDSX xoaddr:$A))>;
 def : Pat<(v2i64 (PPCldsplat xoaddr:$A)),
           (v2i64 (LXVDSX xoaddr:$A))>;
 
 // Build vectors of floating point converted to i64.
 def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
           (v2i64 (XXPERMDIs
                    (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;

 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
 

llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
 ; RUN:  --check-prefix=CHECK-P7
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 
 define signext i32 @f32toi32(float %a) {
 entry:
   %0 = bitcast float %a to i32
   ret i32 %0
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwa 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stfd 1,
 ; CHECK-P7: ld 3,

 
 define zeroext i32 @f32toi32u(float %a) {
 entry:
   %0 = bitcast float %a to i32
   ret i32 %0
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwz 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64u(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stfd 1,
 ; CHECK-P7: ld 3,

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 }
 
 ; Float indexed
 
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
 ; CHECK-LABEL: testFloat1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpspn vs0, f1
-; CHECK-NEXT:    extsw r3, r6
-; CHECK-NEXT:    slwi r3, r3, 2
-; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-NEXT:    mffprwz r4, f0
-; CHECK-NEXT:    vinswrx v2, r3, r4
+; CHECK-NEXT:    extsw r4, r6
+; CHECK-NEXT:    slwi r4, r4, 2
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    vinswrx v2, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testFloat1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpspn vs0, f1
-; CHECK-BE-NEXT:    extsw r3, r6
-; CHECK-BE-NEXT:    slwi r3, r3, 2
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    vinswlx v2, r3, r4
+; CHECK-BE-NEXT:    extsw r4, r6
+; CHECK-BE-NEXT:    slwi r4, r4, 2
+; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat1:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfsx f1, r4, r3

 ; CHECK-P9-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
   %0 = bitcast i32* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }