[PowerPC] Improve f32 to i32 bitcast code gen

[Conanap]

Summary

The code gen for f32 to i32 bitcast is not currently the most efficient. For example:

int foo(float f) {
  return *(int*)&f;
}

Generates:

xscvdpspn vs0, f1
xxsldwi vs0, vs0, vs0, 3
mffprwz	r3, f0

However, xxsldwi is actually not needed as xscvdpspn already splats the value.

This patch removes that instruction for this specific code gen.

[nemanjai]

This will still produce a redundant XXSLDWI:

vector float test(vector float a, float b) {
  a[3] = b;
  return a;
}

when compiled with -mcpu=pwr9.

[Conanap]

Updated to remove uncessary xrsp and other xxsldwi as well

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2820

These COPY_TO_REGCLASS should probably be SUBREG_TO_REG (all of them by the looks of it).

4376

I am not really seeing the tests for these.
Can we add some tests of the form

vector float test(vector float a, double b) {
  a[1] = b;
  return a;
}

[Conanap]

Updated COPY_TO_REGCLASS to SUBREG_TO_REG, added a test case.

[nemanjai]

Please add the missing BE handling.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2821

Although it is accurate that this specific instruction clears the other bits, all the other uses of SUBREG_TO_REG in the back end use (i64 1) and I don't think it is particularly useful to part with that here.

4376

These also need to be added for big endian subtargets.

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

741

Notice that this still generates the undesired code due to missing the new patterns for big endian subtargets.

[Conanap]

Added big-endian pattern

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst),
                                  (select i1:$cond, f32:$T, f32:$F))]>;
 }
 }
 
 //----------------------------- DAG Definitions ------------------------------//
 
 // Output dag used to bitcast f32 to i32 and f64 to i64
 def Bitcast {
-  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI (XSCVDPSPN $A),
-                      (XSCVDPSPN $A), 3), sub_64)));
+  dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
   dag DblToLong = (i64 (MFVSRD $A));
 }
 
 def FpMinMax {
   dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC),
                                           (COPY_TO_REGCLASS $B, VSFRC)),
                                  VSSRC);
   dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC),
dag BE_32B_VDWORD_PERM_VEC = (v16i8 (LVSL (i32 ZERO),
                                         (RLWINM (ANDI_rec $Idx, 1), 3, 0, 28)));
   dag BE_32B_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
                                       (v16i8 (COPY_TO_REGCLASS $S, VRRC)),
                                       BE_32B_VDWORD_PERM_VEC));
   dag BE_32B_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_32B_VDOUBLE_PERMUTE, VSRC);
 }
 
 def AlignValues {
-  dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
+  dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B));
   dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64);
 }
 
 // Integer extend helper dags 32 -> 64
 def AnyExts {
   dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);
   dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);
   dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);

 defm : ScalToVecWPermute<
   v4i32, FltToIntLoad.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;
 defm : ScalToVecWPermute<
   v4i32, FltToUIntLoad.A,
   (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1),
   (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>;
+def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)),
+                               (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))),
+          (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>;
+
 def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
           (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
 def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)),
           (v2f64 (LXVDSX ForceXForm:$A))>;
 def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)),
           (v2i64 (LXVDSX ForceXForm:$A))>;
 
 // Build vectors of floating point converted to i64.
def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
 
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;
+
 // Scalar stores of i8
 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst),
           (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), ForceXForm:$dst)>;
 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), ForceXForm:$dst),
           (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), ForceXForm:$dst)>;
 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), ForceXForm:$dst),
           (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), ForceXForm:$dst)>;
 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), ForceXForm:$dst),

 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>;
 def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)),
           (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>;
 def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)),
           (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>;
 
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>;
+def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)),
+          (v4f32 (XXINSERTW v4f32:$A,
+                  (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>;
+
 def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)),
           (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>;
 def : Pat<(PPCst_vec_be v8i16:$rS, ForceXForm:$dst),
           (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), ForceXForm:$dst)>;
 
 def : Pat<(v16i8 (PPCld_vec_be ForceXForm:$src)),
           (COPY_TO_REGCLASS (LXVB16X ForceXForm:$src), VRRC)>;
 def : Pat<(PPCst_vec_be v16i8:$rS, ForceXForm:$dst),

llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll

entry:
   %conv = uitofp i32 %vecext to double
   ret double %conv
 }
 
 define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 ; CHECK-64-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    xscvdpspn 0, 1
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 ; CHECK-64-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    xscvdpspn 0, 1
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 4
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 1
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 ; CHECK-64-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    xscvdpspn 0, 1
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 2
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 ; CHECK-64-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    xscvdpspn 0, 1
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 12
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 12
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 3
   ret <4 x float> %vecins
 }
 
 define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {

llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

entry:
   ret <2 x i64> %vecins
 }
 
 ; Float indexed
 
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testFloat1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    rlwinm 3, 4, 2, 28, 29
-; CHECK-64-NEXT:    addi 4, 1, -16
+; CHECK-64-DAG:     rlwinm 3, 4, 2, 28, 29
+; CHECK-64-DAG:     addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfsx 1, 4, 3
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stfsx 1, 4, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloat1:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
-; CHECK-64-P10-NEXT:    extsw 3, 4
-; CHECK-64-P10-NEXT:    slwi 3, 3, 2
-; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
-; CHECK-64-P10-NEXT:    mffprwz 4, 0
-; CHECK-64-P10-NEXT:    vinswlx 2, 3, 4
+; CHECK-64-P10-NEXT:    extsw 4, 4
+; CHECK-64-P10-NEXT:    slwi 4, 4, 2
+; CHECK-64-P10-NEXT:    mffprwz 3, 0
+; CHECK-64-P10-NEXT:    vinswlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testFloat1:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
-; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-P10-NEXT:    mffprwz 3, 0
 ; CHECK-32-P10-NEXT:    vinswlx 2, 4, 3
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
   ret <4 x float> %vecins
 }
 
 define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lwz 6, 0(3)
-; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
-; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
+; CHECK-64-DAG:     addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    lwz 3, 1(3)
 ; CHECK-64-NEXT:    stxv 0, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
entry:
   %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
   ret <4 x float> %vecins2
 }
 
 define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
-; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
+; CHECK-64-DAG:    addi 7, 1, -32
 ; CHECK-64-NEXT:    lwzx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-NEXT:    lwzx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29

 }
 
 ; Float immediate
 
 define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {
 ; CHECK-64-LABEL: testFloatImm1:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    xscvdpspn 0, 1
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloatImm1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    xscvdpspn 0, 1
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloatImm1:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    xscvdpspn 0, 1
-; CHECK-64-P10-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-64-P10-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testFloatImm1:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    xscvdpspn 0, 1
-; CHECK-32-P10-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-P10-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
   ret <4 x float> %vecins1
 }
 
 define <4 x float> @testFloatImm2(<4 x float> %a, i32* %b) {
 ; CHECK-64-LABEL: testFloatImm2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lfs 0, 0(3)
 ; CHECK-64-NEXT:    xscvdpspn 0, 0
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-64-NEXT:    lfs 0, 4(3)
 ; CHECK-64-NEXT:    xscvdpspn 0, 0
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloatImm2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfs 0, 0(3)
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    lfs 0, 4(3)
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloatImm2:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    lwz 4, 0(3)
 ; CHECK-64-P10-NEXT:    lwz 3, 4(3)
 ; CHECK-64-P10-NEXT:    vinsw 2, 4, 0

 define <4 x float> @testFloatImm3(<4 x float> %a, i32* %b) {
 ; CHECK-64-LABEL: testFloatImm3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 4, 4
 ; CHECK-64-NEXT:    lfsx 0, 3, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    rldic 4, 4, 38, 25
 ; CHECK-64-NEXT:    xscvdpspn 0, 0
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-64-NEXT:    lfsx 0, 3, 4
 ; CHECK-64-NEXT:    xscvdpspn 0, 0
-; CHECK-64-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-64-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloatImm3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 4, 4
 ; CHECK-32-NEXT:    lfsx 0, 3, 4
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 0
 ; CHECK-32-NEXT:    lfs 0, 0(3)
 ; CHECK-32-NEXT:    xscvdpspn 0, 0
-; CHECK-32-NEXT:    xxsldwi 0, 0, 0, 3
 ; CHECK-32-NEXT:    xxinsertw 34, 0, 8
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testFloatImm3:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    plwz 4, 262144(3), 0
 ; CHECK-64-P10-NEXT:    vinsw 2, 4, 0
 ; CHECK-64-P10-NEXT:    li 4, 1
entry:
   ret <4 x float> %vecins2
 }
 
 ; Double indexed
 
 define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testDouble1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    rlwinm 3, 4, 3, 28, 28
+; CHECK-64:         rlwinm 3, 4, 3, 28, 28
 ; CHECK-64-NEXT:    addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfdx 1, 4, 3
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDouble1:
 ; CHECK-32:       # %bb.0: # %entry

 ; CHECK-64-P10-NEXT:    extsw 4, 4
 ; CHECK-64-P10-NEXT:    mffprd 3, 1
 ; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble1:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-NEXT:    addi 4, 1, -16
-; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-DAG:     addi 4, 1, -16
+; CHECK-32-P10-DAG:     rlwinm 3, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-P10-NEXT:    lxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 6, 0(3)
-; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
-; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-DAG:         rlwinm 4, 4, 3, 28, 28
+; CHECK-64-DAG:    addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    ldx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 0, -16(1)

 ; CHECK-64-P10-NEXT:    extsw 4, 5
 ; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble2:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    lfd 0, 0(3)
-; CHECK-32-P10-NEXT:    addi 6, 1, -32
-; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-DAG:     addi 6, 1, -32
+; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stxv 34, -32(1)
 ; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-P10-NEXT:    lxv 0, -32(1)
 ; CHECK-32-P10-NEXT:    lfd 1, 1(3)
 ; CHECK-32-P10-NEXT:    addi 3, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 0, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
entry:
   %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
   ret <2 x double> %vecins2
 }
 
 define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
-; CHECK-64-NEXT:    addi 7, 1, -32
+; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
+; CHECK-64-DAG:     addi 7, 1, -32
 ; CHECK-64-NEXT:    ldx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-NEXT:    ldx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28

llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
 ; RUN:  --check-prefix=CHECK-P7
 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
 
 define signext i32 @f32toi32(float %a) {
 entry:
   %0 = bitcast float %a to i32
   ret i32 %0
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwa 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stfd 1,
 ; CHECK-P7: ld 3,

 
 define zeroext i32 @f32toi32u(float %a) {
 entry:
   %0 = bitcast float %a to i32
   ret i32 %0
 ; CHECK-P7: stfs 1,
 ; CHECK-P7: lwz 3,
 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
-; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
-; CHECK: mffprwz 3, [[SHIFTREG]]
+; CHECK-NOT: xxsldwi
+; CHECK: mffprwz 3, [[CONVREG]]
 }
 
 define i64 @f64toi64u(double %a) {
 entry:
   %0 = bitcast double %a to i64
   ret i64 %0
 ; CHECK-P7: stfd 1,
 ; CHECK-P7: ld 3,

llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll

entry:
   %conv = uitofp i32 %vecext to double
   ret double %conv
 }
 
 define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
 ; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
 ; CHECK: xxinsertw 34, 0, 12
 ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
 ; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
 ; CHECK-BE: xxinsertw 34, 0, 0
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
 ; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
 ; CHECK: xxinsertw 34, 0, 8
 ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
 ; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
 ; CHECK-BE: xxinsertw 34, 0, 4
   %vecins = insertelement <4 x float> %a, float %b, i32 1
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
 ; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
 ; CHECK: xxinsertw 34, 0, 4
 ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
 ; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
 ; CHECK-BE: xxinsertw 34, 0, 8
   %vecins = insertelement <4 x float> %a, float %b, i32 2
   ret <4 x float> %vecins
 }
 
 define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
 ; CHECK: xscvdpspn 0, 1
-; CHECK: xxsldwi 0, 0, 0, 3
 ; CHECK: xxinsertw 34, 0, 0
 ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
 ; CHECK-BE: xscvdpspn 0, 1
-; CHECK-BE: xxsldwi 0, 0, 0, 3
 ; CHECK-BE: xxinsertw 34, 0, 12
   %vecins = insertelement <4 x float> %a, float %b, i32 3
   ret <4 x float> %vecins
 }
 
 define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
 entry:
 ; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <4 x float> @s2v_test_f1(float* nocapture readonly %f64, <4 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f1:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lfs f0, 0(r3)
 ; P9LE-NEXT:    xscvdpspn vs0, f0
-; P9LE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; P9LE-NEXT:    xxinsertw v2, vs0, 12
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f1:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lfs f0, 0(r3)
 ; P9BE-NEXT:    xscvdpspn vs0, f0
-; P9BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; P9BE-NEXT:    xxinsertw v2, vs0, 0
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f1:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI5_0@toc@l

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 }
 
 ; Float indexed
 
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
 ; CHECK-LABEL: testFloat1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpspn vs0, f1
-; CHECK-NEXT:    extsw r3, r6
-; CHECK-NEXT:    slwi r3, r3, 2
-; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-NEXT:    mffprwz r4, f0
-; CHECK-NEXT:    vinswrx v2, r3, r4
+; CHECK-NEXT:    extsw r4, r6
+; CHECK-NEXT:    slwi r4, r4, 2
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    vinswrx v2, r4, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testFloat1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpspn vs0, f1
-; CHECK-BE-NEXT:    extsw r3, r6
-; CHECK-BE-NEXT:    slwi r3, r3, 2
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    vinswlx v2, r3, r4
+; CHECK-BE-NEXT:    extsw r4, r6
+; CHECK-BE-NEXT:    slwi r4, r4, 2
+; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat1:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfsx f1, r4, r3

 }
 
 ; Float immediate
 
 define <4 x float> @testFloatImm1(<4 x float> %a, float %b) {
 ; CHECK-LABEL: testFloatImm1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpspn vs0, f1
-; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-NEXT:    xxinsertw v2, vs0, 12
 ; CHECK-NEXT:    xxinsertw v2, vs0, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testFloatImm1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpspn vs0, f1
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-BE-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-BE-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloatImm1:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f1
-; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-P9-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 0
   %vecins1 = insertelement <4 x float> %vecins, float %b, i32 2
   ret <4 x float> %vecins1
 }

 ; CHECK-BE-NEXT:    lwz r3, 4(r5)
 ; CHECK-BE-NEXT:    vinsw v2, r3, 8
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloatImm2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lfs f0, 0(r5)
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
-; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-P9-NEXT:    lfs f0, 4(r5)
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
-; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-P9-NEXT:    blr
 entry:
   %0 = bitcast i32* %b to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 1
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4
   %vecins = insertelement <4 x float> %a, float %2, i32 0

 ;
 ; CHECK-P9-LABEL: testFloatImm3:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lis r3, 4
 ; CHECK-P9-NEXT:    lfsx f0, r5, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    rldic r3, r3, 38, 25
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
-; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-P9-NEXT:    lfsx f0, r5, r3
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
-; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-P9-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-P9-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 65536
   %0 = bitcast i32* %add.ptr to float*
   %add.ptr1 = getelementptr inbounds i32, i32* %b, i64 68719476736
   %1 = bitcast i32* %add.ptr1 to float*
   %2 = load float, float* %0, align 4

 entry:
   %add.ptr = getelementptr inbounds i32, i32* %b, i64 68719476736
   %0 = bitcast i32* %add.ptr to double*
   %1 = load double, double* %0, align 8
   %vecins = insertelement <2 x double> %a, double %1, i32 0
   ret <2 x double> %vecins
 }
 
+define dso_local <4 x float> @testInsertDoubleToFloat(<4 x float> %a, double %b) local_unnamed_addr #0 {
+; CHECK-LABEL: testInsertDoubleToFloat:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpsp f0, f1
+; CHECK-NEXT:    xxinsertw v2, vs0, 8
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: testInsertDoubleToFloat:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xscvdpsp f0, f1
+; CHECK-BE-NEXT:    xxinsertw v2, vs0, 4
+; CHECK-BE-NEXT:    blr
+;
+; CHECK-P9-LABEL: testInsertDoubleToFloat:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    xscvdpsp f0, f1
+; CHECK-P9-NEXT:    xxinsertw v2, vs0, 4
+; CHECK-P9-NEXT:    blr
+entry:
+  %conv = fptrunc double %b to float
+  %vecins = insertelement <4 x float> %a, float %conv, i32 1
+  ret <4 x float> %vecins
+}