[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

[Conanap]

Summary

The following example generates code that can be completed in two instructions instead:

void testutof(vector unsigned short a, float *ptr) {
  *ptr = a[0];
}

The patch improves this code gen.

[Conanap]

Added test file

[Conanap]

Rebased and fixed indentations

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
             (f128 (XSCVSDQP (EXTRACT_SUBREG
                             (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;
 }
 foreach Idx = 0-3 in {
   def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
             (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
 }
 
-// (Un)Signed HWord vector extract -> QP
+// (Un)Signed HWord vector extract -> QP/DP/SP
 foreach Idx = 0-7 in {
   def : Pat<(f128 (sint_to_fp
                     (i32 (sext_inreg
                            (vector_extract v8i16:$src, Idx), i16)))),
           (f128 (XSCVSDQP (EXTRACT_SUBREG
                             (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
                             sub_64)))>;
   // The SDAG adds the `and` since an `i16` is being extracted as an `i32`.
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v8i16:$src, Idx)), 65535))),
             (f128 (XSCVUDQP (EXTRACT_SUBREG
                               (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfidus
+                   (f64 (PPCmtvsrz
+                          (and (i32 (vector_extract v8i16:$src, Idx)), 65535)
+                        )))),
+            (f32 (XSCVUXDSP (EXTRACT_SUBREG
+                              (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfids
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg (vector_extract v8i16:$src, Idx), i16))
+                        )))),
+          (f32 (XSCVSXDSP (EXTRACT_SUBREG
+                            (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
+                            sub_64)))>;
+  def : Pat<(f64 (PPCfcfidu
+                   (f64 (PPCmtvsrz
+                          (and (i32 (vector_extract v8i16:$src, Idx)), 65535)
+                        )))),
+            (f64 (XSCVUXDDP (EXTRACT_SUBREG
+                              (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>;
+  def : Pat<(f64 (PPCfcfid
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg (vector_extract v8i16:$src, Idx), i16))
+                        )))),
+          (f64 (XSCVSXDDP (EXTRACT_SUBREG
+                            (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)),
+                            sub_64)))>;
 }
 
 // (Un)Signed Byte vector extract -> QP
 foreach Idx = 0-15 in {
   def : Pat<(f128 (sint_to_fp
                     (i32 (sext_inreg (vector_extract v16i8:$src, Idx),
                                      i8)))),
             (f128 (XSCVSDQP (EXTRACT_SUBREG
                               (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v16i8:$src, Idx)), 255))),
             (f128 (XSCVUDQP
                     (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>;
+
+  def : Pat<(f32 (PPCfcfidus
+                   (f64 (PPCmtvsrz
+                          (and (i32 (vector_extract v16i8:$src, Idx)), 255)
+                        )))),
+            (f32 (XSCVUXDSP (EXTRACT_SUBREG
+                              (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfids
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg (vector_extract v16i8:$src, Idx), i8))
+                        )))),
+          (f32 (XSCVSXDSP (EXTRACT_SUBREG
+                            (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
+                            sub_64)))>;
+  def : Pat<(f64 (PPCfcfidu
+                   (f64 (PPCmtvsrz
+                          (and (i32 (vector_extract v16i8:$src, Idx)), 255)
+                        )))),
+            (f64 (XSCVUXDDP (EXTRACT_SUBREG
+                              (VEXTRACTUB !add(Idx, Idx), $src), sub_64)))>;
+  def : Pat<(f64 (PPCfcfid
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg (vector_extract v16i8:$src, Idx), i8))
+                        )))),
+          (f64 (XSCVSXDDP (EXTRACT_SUBREG
+                            (VEXTSH2D (VEXTRACTUB !add(Idx, Idx), $src)),
+                            sub_64)))>;
 }
 
 // Unsiged int in vsx register -> QP
 def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
           (f128 (XSCVUDQP
                   (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>;
 } // HasVSX, HasP9Vector, IsBigEndian, IsPPC64
 

 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),
           (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
 
 foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {
   def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
             (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
 }
 
-// (Un)Signed HWord vector extract -> QP
+// (Un)Signed HWord vector extract -> QP/DP/SP
 // The Nested foreach lists identifies the vector element and corresponding
 // register byte location.
 foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in {
   def : Pat<(f128 (sint_to_fp
                     (i32 (sext_inreg
                            (vector_extract v8i16:$src, !head(Idx)), i16)))),
             (f128 (XSCVSDQP
                     (EXTRACT_SUBREG (VEXTSH2D
                                       (VEXTRACTUH !head(!tail(Idx)), $src)),
                                     sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v8i16:$src, !head(Idx))),
                          65535))),
             (f128 (XSCVUDQP (EXTRACT_SUBREG
                               (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfidus
+                   (f64 (PPCmtvsrz
+                          (and (i32
+                            (vector_extract v8i16:$src, !head(Idx))), 65535)
+                        )))),
+            (f32 (XSCVUXDSP (EXTRACT_SUBREG
+                              (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfids
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg
+                            (vector_extract v8i16:$src, !head(Idx)), i16))
+                        )))),
+            (f32 (XSCVSXDSP
+                    (EXTRACT_SUBREG (VEXTSH2D
+                                      (VEXTRACTUH !head(!tail(Idx)), $src)),
+                                    sub_64)))>;
+  def : Pat<(f64 (PPCfcfidu
+                   (f64 (PPCmtvsrz
+                          (and (i32
+                            (vector_extract v8i16:$src, !head(Idx))), 65535)
+                        )))),
+            (f64 (XSCVUXDDP (EXTRACT_SUBREG
+                              (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>;
+  def : Pat<(f64 (PPCfcfid
+                   (f64 (PPCmtvsra
+                        (i32 (sext_inreg
+                            (vector_extract v8i16:$src, !head(Idx)), i16)))))),
+            (f64 (XSCVSXDDP
+                    (EXTRACT_SUBREG (VEXTSH2D
+                                      (VEXTRACTUH !head(!tail(Idx)), $src)),
+                                    sub_64)))>;
 }
 
-// (Un)Signed Byte vector extract -> QP
+// (Un)Signed Byte vector extract -> QP/DP/SP
 foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7],
                [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in {
   def : Pat<(f128 (sint_to_fp
                     (i32 (sext_inreg
                            (vector_extract v16i8:$src, !head(Idx)), i8)))),
             (f128 (XSCVSDQP
                     (EXTRACT_SUBREG
                       (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)),
                       sub_64)))>;
   def : Pat<(f128 (uint_to_fp
                     (and (i32 (vector_extract v16i8:$src, !head(Idx))),
                          255))),
             (f128 (XSCVUDQP
                     (EXTRACT_SUBREG
                       (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+
+  def : Pat<(f32 (PPCfcfidus
+                   (f64 (PPCmtvsrz
+                          (and (i32
+                            (vector_extract v16i8:$src, !head(Idx))), 255)
+                        )))),
+            (f32 (XSCVUXDSP (EXTRACT_SUBREG
+                              (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+  def : Pat<(f32 (PPCfcfids
+                   (f64 (PPCmtvsra
+                          (i32 (sext_inreg
+                            (vector_extract v16i8:$src, !head(Idx)), i8))
+                        )))),
+            (f32 (XSCVSXDSP
+                    (EXTRACT_SUBREG (VEXTSH2D
+                                      (VEXTRACTUB !head(!tail(Idx)), $src)),
+                                    sub_64)))>;
+  def : Pat<(f64 (PPCfcfidu
+                   (f64 (PPCmtvsrz
+                          (and (i32
+                            (vector_extract v16i8:$src, !head(Idx))), 255)
+                        )))),
+            (f64 (XSCVUXDDP (EXTRACT_SUBREG
+                              (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>;
+  def : Pat<(f64 (PPCfcfidu
+                   (f64 (PPCmtvsra
+                        (i32 (sext_inreg
+                            (vector_extract v16i8:$src, !head(Idx)), i8)))))),
+            (f64 (XSCVSXDDP
+                    (EXTRACT_SUBREG (VEXTSH2D
+                                      (VEXTRACTUB !head(!tail(Idx)), $src)),
+                                    sub_64)))>;
+
+  def : Pat<(f64 (PPCfcfid
+                   (f64 (PPCmtvsra
+                        (i32 (sext_inreg
+                            (vector_extract v16i8:$src, !head(Idx)), i8)))))),
+            (f64 (XSCVSXDDP
+                    (EXTRACT_SUBREG (VEXTSH2D
+                                      (VEXTRACTUH !head(!tail(Idx)), $src)),
+                                    sub_64)))>;
 }
 
 // Unsiged int in vsx register -> QP
 def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))),
           (f128 (XSCVUDQP
                   (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>;
 } // HasVSX, HasP9Vector, IsLittleEndian
 

llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
 ; RUN:   -check-prefix=P9BE
 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
 ; RUN:   -check-prefix=P9LE
 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
 ; RUN:   -check-prefix=P8BE
 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
 ; RUN:   -check-prefix=P8LE
 define dso_local <2 x double> @test1(<8 x i16> %a) {
 ; P9BE-LABEL: test1:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    mtfprwz f0, r3
-; P9BE-NEXT:    li r3, 2
-; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    xscvuxddp f0, f0
-; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    mtfprwz f1, r3
-; P9BE-NEXT:    xscvuxddp f1, f1
+; P9BE-NEXT:    vextractuh v3, v2, 0
+; P9BE-NEXT:    vextractuh v2, v2, 2
+; P9BE-NEXT:    xscvuxddp f0, v3
+; P9BE-NEXT:    xscvuxddp f1, v2
 ; P9BE-NEXT:    xxmrghd v2, vs0, vs1
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: test1:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    li r3, 0
-; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    clrlwi r3, r3, 16
-; P9LE-NEXT:    mtfprwz f0, r3
-; P9LE-NEXT:    li r3, 2
-; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    xscvuxddp f0, f0
-; P9LE-NEXT:    clrlwi r3, r3, 16
-; P9LE-NEXT:    mtfprwz f1, r3
-; P9LE-NEXT:    xscvuxddp f1, f1
+; P9LE-NEXT:    vextractuh v3, v2, 14
+; P9LE-NEXT:    vextractuh v2, v2, 12
+; P9LE-NEXT:    xscvuxddp f0, v3
+; P9LE-NEXT:    xscvuxddp f1, v2
 ; P9LE-NEXT:    xxmrghd v2, vs1, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    mfvsrd r3, v2
 ; P8BE-NEXT:    rldicl r4, r3, 16, 48
 ; P8BE-NEXT:    rldicl r3, r3, 32, 48

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P8-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    clrlwi r3, r3, 16
-; CHECK-P9-NEXT:    mtfprwz f0, r3
-; CHECK-P9-NEXT:    li r3, 2
-; CHECK-P9-NEXT:    xscvuxdsp f0, f0
-; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    clrlwi r3, r3, 16
+; CHECK-P9-NEXT:    vextractuh v3, v2, 14
+; CHECK-P9-NEXT:    vextractuh v2, v2, 12
+; CHECK-P9-NEXT:    xscvuxdsp f0, v3
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT:    mtfprwz f0, r3
-; CHECK-P9-NEXT:    xscvuxdsp f0, f0
+; CHECK-P9-NEXT:    xscvuxdsp f0, v2
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 3
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    li r3, 2
-; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    clrlwi r3, r3, 16
-; CHECK-BE-NEXT:    mtfprwz f0, r3
-; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    xscvuxdsp f0, f0
-; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    clrlwi r3, r3, 16
+; CHECK-BE-NEXT:    vextractuh v3, v2, 2
+; CHECK-BE-NEXT:    vextractuh v2, v2, 0
+; CHECK-BE-NEXT:    xscvuxdsp f0, v3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtfprwz f0, r3
-; CHECK-BE-NEXT:    xscvuxdsp f0, f0
+; CHECK-BE-NEXT:    xscvuxdsp f0, v2
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64

 ; CHECK-P8-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    extsh r3, r3
-; CHECK-P9-NEXT:    mtfprwa f0, r3
-; CHECK-P9-NEXT:    li r3, 2
-; CHECK-P9-NEXT:    xscvsxdsp f0, f0
-; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
-; CHECK-P9-NEXT:    extsh r3, r3
+; CHECK-P9-NEXT:    vextractuh v3, v2, 14
+; CHECK-P9-NEXT:    vextractuh v2, v2, 12
+; CHECK-P9-NEXT:    vextsh2d v3, v3
+; CHECK-P9-NEXT:    vextsh2d v2, v2
+; CHECK-P9-NEXT:    xscvsxdsp f0, v3
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT:    mtfprwa f0, r3
-; CHECK-P9-NEXT:    xscvsxdsp f0, f0
+; CHECK-P9-NEXT:    xscvsxdsp f0, v2
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 3
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    li r3, 2
-; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    mtfprwa f0, r3
-; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    xscvsxdsp f0, f0
-; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
-; CHECK-BE-NEXT:    extsh r3, r3
+; CHECK-BE-NEXT:    vextractuh v3, v2, 2
+; CHECK-BE-NEXT:    vextractuh v2, v2, 0
+; CHECK-BE-NEXT:    vextsh2d v3, v3
+; CHECK-BE-NEXT:    vextsh2d v2, v2
+; CHECK-BE-NEXT:    xscvsxdsp f0, v3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtfprwa f0, r3
-; CHECK-BE-NEXT:    xscvsxdsp f0, f0
+; CHECK-BE-NEXT:    xscvsxdsp f0, v2
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-P8-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    clrlwi r3, r3, 24
-; CHECK-P9-NEXT:    mtfprwz f0, r3
-; CHECK-P9-NEXT:    li r3, 1
-; CHECK-P9-NEXT:    xscvuxdsp f0, f0
-; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    clrlwi r3, r3, 24
+; CHECK-P9-NEXT:    vextractub v3, v2, 15
+; CHECK-P9-NEXT:    vextractub v2, v2, 14
+; CHECK-P9-NEXT:    xscvuxdsp f0, v3
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT:    mtfprwz f0, r3
-; CHECK-P9-NEXT:    xscvuxdsp f0, f0
+; CHECK-P9-NEXT:    xscvuxdsp f0, v2
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 3
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    li r3, 1
-; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    clrlwi r3, r3, 24
-; CHECK-BE-NEXT:    mtfprwz f0, r3
-; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    xscvuxdsp f0, f0
-; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    clrlwi r3, r3, 24
+; CHECK-BE-NEXT:    vextractub v3, v2, 2
+; CHECK-BE-NEXT:    vextractub v2, v2, 0
+; CHECK-BE-NEXT:    xscvuxdsp f0, v3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtfprwz f0, r3
-; CHECK-BE-NEXT:    xscvuxdsp f0, f0
+; CHECK-BE-NEXT:    xscvuxdsp f0, v2
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64

 ; CHECK-P8-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, v2
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
-; CHECK-P9-NEXT:    li r3, 0
-; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    extsb r3, r3
-; CHECK-P9-NEXT:    mtfprwa f0, r3
-; CHECK-P9-NEXT:    li r3, 1
-; CHECK-P9-NEXT:    xscvsxdsp f0, f0
-; CHECK-P9-NEXT:    vextubrx r3, r3, v2
-; CHECK-P9-NEXT:    extsb r3, r3
+; CHECK-P9-NEXT:    vextractub v3, v2, 15
+; CHECK-P9-NEXT:    vextractub v2, v2, 14
+; CHECK-P9-NEXT:    vextsh2d v3, v3
+; CHECK-P9-NEXT:    vextsh2d v2, v2
+; CHECK-P9-NEXT:    xscvsxdsp f0, v3
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 3
-; CHECK-P9-NEXT:    mtfprwa f0, r3
-; CHECK-P9-NEXT:    xscvsxdsp f0, f0
+; CHECK-P9-NEXT:    xscvsxdsp f0, v2
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 3
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    li r3, 1
-; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    mtfprwa f0, r3
-; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    xscvsxdsp f0, f0
-; CHECK-BE-NEXT:    vextublx r3, r3, v2
-; CHECK-BE-NEXT:    extsb r3, r3
+; CHECK-BE-NEXT:    vextractub v3, v2, 2
+; CHECK-BE-NEXT:    vextractub v2, v2, 0
+; CHECK-BE-NEXT:    vextsh2d v3, v3
+; CHECK-BE-NEXT:    vextsh2d v2, v2
+; CHECK-BE-NEXT:    xscvsxdsp f0, v3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtfprwa f0, r3
-; CHECK-BE-NEXT:    xscvsxdsp f0, f0
+; CHECK-BE-NEXT:    xscvsxdsp f0, v2
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64