[SCEV] Add a ad-hoc pattern on isImpliedCondBalancedTypes

[jaykang10]

Summary

I have seen some cases which SCEV's isImpliedCond returns false.

It looks `isImpliedCond' has no patterns for case which the FoundLHS or FoundRHS is AddRec and the LHS and RHS are not AddRec.

In order to handle this case, we can use below one.

If FoundLHS is AddRec and FoundPred is EQ, we can say

The min value of FoundRHS is AddRec's start value if and only if "AddRec == FoundRHS" is true.

It means we can use "FoundRHS >= AddRec's start value" for "AddRec == FoundRHS".

This changes helps IRCE pass handles cascaded sibling loops.

[jaykang10]

@reames I am aiming to handle more cases on IRCE pass. If you think SCEV is not good place for this change, please let me know. I could move this change to IRCE pass.

[jaykang10]

Fixed a typo

[nikic]

llvm/lib/Analysis/ScalarEvolution.cpp

10468

I find it really hard to understand this is doing based on the description. I believe the claim is that
A: Start s<= FoundRHS --> LHS s< RHS
implies
B: <Start,+,Step> == FoundRHS --> LHS s< RHS.

A sufficient condition for that to hold would be that <Start,+,Step> == FoundRHS implies Start s<= FoundRHS. I assume that was your line of reasoning.

However, this is clearly not true without further legality checks. You need to at least require that the addrec is nsw, and that the step is non-negative.

[jaykang10]

llvm/lib/Analysis/ScalarEvolution.cpp

10468

I am sorry for poor description...

A sufficient condition for that to hold would be that <Start,+,Step> == FoundRHS implies Start s<= FoundRHS. I assume that was your line of reasoning.

Yep, it is exactly correct.

However, this is clearly not true without further legality checks. You need to at least require that the addrec is nsw, and that the step is non-negative.

You are right!!! Let me add legality checks with nsw and non-negative step.

[jaykang10]

Following the comment of @nikic, added checks for negative step and nsw/nuw.

[jaykang10]

@nikic I have run llvm-testsuite to check correctness. It seems fine.

[jaykang10]

Followed clang-format

[jaykang10]

@nikic If you need something more, please let me know.

[nikic]

This needs better test coverage for the various conditions in the code, like step sign, nowrap flags, possibly predicates. Either as IR test cases, or as unit tests.

llvm/lib/Analysis/ScalarEvolution.cpp

10484

As you are working with signed predicates here, you need nsw. nuw is not enough. Of course, you could handle the analogous case with unsigned predicates, in which case you need nuw (and only nuw, the step sign doesn't matter in that case).

[jaykang10]

In D100566#2706635, @nikic wrote:

This needs better test coverage for the various conditions in the code, like step sign, nowrap flags, possibly predicates. Either as IR test cases, or as unit tests.

@nikic I appreciate your comments. I have updated the predicates and added unit tests for them. Please check it.

llvm/lib/Analysis/ScalarEvolution.cpp

10484

You are right! I will update it.

[jaykang10]

Following comments of @nikic, updated code and added unit tests.

[nikic]

llvm/lib/Analysis/ScalarEvolution.cpp

10486

This still isn't right: the required nowrap flag depends on the predicate. If you have NewFoundPred = ICMP_SLE, then you need nsw. If you have NewFoundPred = ICMP_ULE, then you need nuw.

[jaykang10]

llvm/lib/Analysis/ScalarEvolution.cpp

10486

Oops! sorry, you are right! It looks the unsigned predicate with constant is transformed with SimplifyICmpOperands earlier. Let's just handle signed case.

[jaykang10]

Following comment from @nikic, updated code.

[jaykang10]

@nikic If you need something more for this change, please let me know.

Additionally, if possible, can you also review https://reviews.llvm.org/D101409 please?

[nikic]

llvm/lib/Analysis/ScalarEvolution.cpp

10477

As far as I can tell, the actual Pred is not relevant -- this should be correct independently of the used Pred, right? If so, I think it would be better to drop those checks and do something like this:

if (isa<SCEVAddRecExpr>(FoundRHS) && !isa<SCEVAddRecExpr>(FoundLHS)) {
  std::swap(FoundLHS, FoundRHS);
  std::swap(LHS, RHS);
  Pred = ICmpInst::getSwappedPredicate(Pred);
}

if (const auto *AddRec = dyn_cast<SCEVAddRecExpr>(FoundLHS)) {

Though I'm also wondering why we need to handle the case of AddRec in FoundRHS -- normally, AddRecs are canonicalized to the left-hand side. What is breaking the canonicalization here?

10486

Can you please add a test for the unsigned case? Looking at SimplifyICmpOperands, it's not really clear to me why it would already be handled.

10489

You can just return the isImpliedCondBalancedTypes result here, no need for separate return true / return false.

10491

AddRec->hasNoSignedWrap() would be more idiomatic.

llvm/test/Transforms/IRCE/sibling_loops.ll

11

This test is over-reduced. It's best to avoid undef values, as it's very easy for tests to get broken by unrelated changes.

llvm/unittests/Analysis/ScalarEvolutionTest.cpp

1426 ↗

(On Diff #340477)

We should also have a negative test without nsw flag.

1473 ↗

(On Diff #340477)

More typically spelled ICmp...

[jaykang10]

llvm/lib/Analysis/ScalarEvolution.cpp

10477

As far as I can tell, the actual Pred is not relevant -- this should be correct independently of the used Pred, right? If so, I think it would be better to drop those checks and do something like this:

if (isa<SCEVAddRecExpr>(FoundRHS) && !isa<SCEVAddRecExpr>(FoundLHS)) {
  std::swap(FoundLHS, FoundRHS);
  std::swap(LHS, RHS);
  Pred = ICmpInst::getSwappedPredicate(Pred);
}

if (const auto *AddRec = dyn_cast<SCEVAddRecExpr>(FoundLHS)) {

You are right.

Though I'm also wondering why we need to handle the case of AddRec in FoundRHS -- normally, AddRecs are canonicalized to the left-hand side. What is breaking the canonicalization here?

It is just conservative check. If AddRrecs is always canonicalized to the left-hand side, we do not need check FoundRHS. From below unit tests, when I call the isImpliedCond directly, I was able to see the FoundRHS is AddRec. If it is not problem, I will remove above code.

10486

Yep, I will add a unit test which is named with ImpliedCondWithAddRecNUW. You can see it on the unit test. If the unit test is wrong for unsigned, please let me know.

10489

You are right! I will update it.

10491

Yep, I will update it.

llvm/test/Transforms/IRCE/sibling_loops.ll

11

Yep, you are right. Next time, I will be careful. This test aimed to show people the impact of IRCE pass with this SCEV change. I have started the discussion of IRCE pass so I would like to remove this test from this SCEV change now. I am sorry for inconvenience.

llvm/unittests/Analysis/ScalarEvolutionTest.cpp

1426 ↗

(On Diff #340477)

Yep, I will add it.

1473 ↗

(On Diff #340477)

Yep, I will update it.

[jaykang10]

Following comments of @nikic, updated code and added tests.

llvm/lib/Analysis/ScalarEvolution.cpp

bool ScalarEvolution::isImpliedCondBalancedTypes(
   }
 
   // Check whether the actual condition is beyond sufficient.
   if (FoundPred == ICmpInst::ICMP_EQ)
     if (ICmpInst::isTrueWhenEqual(Pred))
       if (isImpliedCondOperands(Pred, LHS, RHS, FoundLHS, FoundRHS, Context))
         return true;
   if (Pred == ICmpInst::ICMP_NE)
     if (!ICmpInst::isTrueWhenEqual(FoundPred))
       if (isImpliedCondOperands(FoundPred, LHS, RHS, FoundLHS, FoundRHS,
                                 Context))
         return true;
 
+  // If FoundLHS is AddRec and FoundPred is EQ, we can say that the min value of
+  // FoundRHS is AddRec's start value if and only if "AddRec == FoundRHS" is
+  // true. It means we can use "FoundRHS >= AddRec's start value".
+  if (FoundPred == ICmpInst::ICMP_EQ) {
+    bool FoundCandidate = false;
+    if (Pred == ICmpInst::ICMP_SGT && isa<SCEVAddRecExpr>(FoundRHS)) {
+      std::swap(FoundLHS, FoundRHS);
+      std::swap(LHS, RHS);
+      Pred = ICmpInst::getSwappedPredicate(Pred);
+      FoundCandidate = true;
+    } else if (Pred == ICmpInst::ICMP_SLT && isa<SCEVAddRecExpr>(FoundLHS))
+      FoundCandidate = true;
+
+    if (FoundCandidate) {
+      auto *AddRec = cast<SCEVAddRecExpr>(FoundLHS);
+      auto *StepCst = dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*this));
+      if (StepCst && (AddRec->getNoWrapFlags(SCEV::FlagNSW) ||
+                      AddRec->getNoWrapFlags(SCEV::FlagNUW))) {
+        if (!StepCst->getValue()->isNegative()) {
+          auto *NewFoundLHS = cast<SCEVAddRecExpr>(FoundLHS)->getStart();
+          auto NewFoundPred = ICmpInst::ICMP_SLE;
+          if (isImpliedCondBalancedTypes(Pred, LHS, RHS, NewFoundPred,
+                                         NewFoundLHS, FoundRHS, Context))
+            return true;
+        }
+      }
+    }
+  }
+
   // Otherwise assume the worst.
   return false;
 }
 
 bool ScalarEvolution::splitBinaryAdd(const SCEV *Expr,
                                      const SCEV *&L, const SCEV *&R,
                                      SCEV::NoWrapFlags &Flags) {
   const auto *AE = dyn_cast<SCEVAddExpr>(Expr);

llvm/test/Transforms/IRCE/sibling_loops.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -irce -irce-skip-profitability-checks -irce-print-changed-loops -S < %s 2>&1 | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: irce: in function test: constrained Loop at depth 1 containing: %12<header>,%15,%16<latch><exiting>
+
+define dso_local void @test() local_unnamed_addr #0 {
+  %1 = zext i32 undef to i64
+  br label %2
+
+2:                                                ; preds = %4, %0
+  %3 = phi i64 [ %5, %4 ], [ 1, %0 ]
+  br label %4
+
+4:                                                ; preds = %2
+  %5 = add nuw nsw i64 %3, 1
+  %6 = icmp eq i64 %5, %1
+  br i1 %6, label %7, label %2
+
+7:                                                ; preds = %4
+  br label %8
+
+8:                                                ; preds = %12, %7
+  %9 = phi i64 [ %13, %12 ], [ 1, %7 ]
+  %10 = icmp slt i64 %9, undef
+  br i1 %10, label %11, label %12
+
+11:                                               ; preds = %8
+  br label %12
+
+12:                                               ; preds = %11, %8
+  %13 = add nuw nsw i64 %9, 1
+  %14 = icmp eq i64 %13, %1
+  br i1 %14, label %15, label %8
+
+15:                                               ; preds = %12
+  ret void
+}
+
+attributes #0 = { "target-features"="+neon" }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git b601c6719226fb83c43dae62a581e5ee08bfb169)"}

llvm/test/Transforms/IndVarSimplify/lftr-pr20680.ll

 ; CHECK:       for.cond2.loopexit.us.us:
 ; CHECK-NEXT:    br i1 true, label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_US_LCSSA_US:%.*]], label [[FOR_BODY3_US_US]]
 ; CHECK:       for.inc.lr.ph.us.us:
 ; CHECK-NEXT:    br label [[FOR_INC_US_US:%.*]]
 ; CHECK:       for.cond8.for.cond2.loopexit_crit_edge.us.us:
 ; CHECK-NEXT:    store i32 1, i32* @b, align 4
 ; CHECK-NEXT:    br label [[FOR_COND2_LOOPEXIT_US_US]]
 ; CHECK:       for.inc.us.us:
-; CHECK-NEXT:    [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[FOR_INC_LR_PH_US_US]] ], [ [[INC_US_US:%.*]], [[FOR_INC_US_US]] ]
-; CHECK-NEXT:    [[INC_US_US]] = add nsw i32 [[TMP5]], 1
-; CHECK-NEXT:    [[EXITCOND3:%.*]] = icmp ne i32 [[INC_US_US]], 1
-; CHECK-NEXT:    br i1 [[EXITCOND3]], label [[FOR_INC_US_US]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE_US_US:%.*]]
+; CHECK-NEXT:    br i1 true, label [[FOR_INC_US_US]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE_US_US:%.*]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa.us.us-lcssa.us:
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US:%.*]]
 ; CHECK:       for.body3.lr.ph.split.us.split:
 ; CHECK-NEXT:    br label [[FOR_BODY3_US:%.*]]
 ; CHECK:       for.body3.us:
 ; CHECK-NEXT:    br i1 true, label [[COND_FALSE_US:%.*]], label [[COND_END_US:%.*]]
 ; CHECK:       cond.false.us:
 ; CHECK-NEXT:    br label [[COND_END_US]]
 ; CHECK:       cond.end.us:
-; CHECK-NEXT:    [[TMP6:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT:    [[CMP91_US:%.*]] = icmp slt i32 [[TMP6]], 1
+; CHECK-NEXT:    [[TMP5:%.*]] = load i32, i32* @b, align 4
+; CHECK-NEXT:    [[CMP91_US:%.*]] = icmp slt i32 [[TMP5]], 1
 ; CHECK-NEXT:    br i1 [[CMP91_US]], label [[FOR_INC_LR_PH_US:%.*]], label [[FOR_COND2_LOOPEXIT_US:%.*]]
 ; CHECK:       for.inc.us:
-; CHECK-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP6]], [[FOR_INC_LR_PH_US]] ], [ [[INC_US:%.*]], [[FOR_INC_US:%.*]] ]
-; CHECK-NEXT:    [[INC_US]] = add nsw i32 [[TMP7]], 1
-; CHECK-NEXT:    [[EXITCOND2:%.*]] = icmp ne i32 [[INC_US]], 1
-; CHECK-NEXT:    br i1 [[EXITCOND2]], label [[FOR_INC_US]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE_US:%.*]]
+; CHECK-NEXT:    br i1 true, label [[FOR_INC_US:%.*]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE_US:%.*]]
 ; CHECK:       for.cond2.loopexit.us:
 ; CHECK-NEXT:    br i1 false, label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_US_LCSSA:%.*]], label [[FOR_BODY3_US]]
 ; CHECK:       for.inc.lr.ph.us:
 ; CHECK-NEXT:    br label [[FOR_INC_US]]
 ; CHECK:       for.cond8.for.cond2.loopexit_crit_edge.us:
 ; CHECK-NEXT:    store i32 1, i32* @b, align 4
 ; CHECK-NEXT:    br label [[FOR_COND2_LOOPEXIT_US]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa.us.us-lcssa:
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa.us:
 ; CHECK-NEXT:    [[COND_LCSSA_PH_US:%.*]] = phi i32 [ [[DIV]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_US_LCSSA]] ], [ [[DIV]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_US_LCSSA_US]] ]
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE:%.*]]
 ; CHECK:       for.body3.lr.ph.split:
 ; CHECK-NEXT:    br i1 [[TOBOOL]], label [[FOR_BODY3_LR_PH_SPLIT_SPLIT_US:%.*]], label [[FOR_BODY3_LR_PH_SPLIT_FOR_BODY3_LR_PH_SPLIT_SPLIT_CRIT_EDGE:%.*]]
 ; CHECK:       for.body3.lr.ph.split.for.body3.lr.ph.split.split_crit_edge:
 ; CHECK-NEXT:    br label [[FOR_BODY3_LR_PH_SPLIT_SPLIT:%.*]]
 ; CHECK:       for.body3.lr.ph.split.split.us:
 ; CHECK-NEXT:    br label [[FOR_BODY3_US3:%.*]]
 ; CHECK:       for.body3.us3:
 ; CHECK-NEXT:    br i1 false, label [[COND_FALSE_US4:%.*]], label [[COND_END_US5:%.*]]
 ; CHECK:       cond.false.us4:
 ; CHECK-NEXT:    br label [[COND_END_US5]]
 ; CHECK:       cond.end.us5:
-; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT:    [[CMP91_US7:%.*]] = icmp slt i32 [[TMP8]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = load i32, i32* @b, align 4
+; CHECK-NEXT:    [[CMP91_US7:%.*]] = icmp slt i32 [[TMP6]], 1
 ; CHECK-NEXT:    br i1 [[CMP91_US7]], label [[FOR_INC_LR_PH_US12:%.*]], label [[FOR_COND2_LOOPEXIT_US11:%.*]]
 ; CHECK:       for.inc.us8:
-; CHECK-NEXT:    [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[FOR_INC_LR_PH_US12]] ], [ [[INC_US9:%.*]], [[FOR_INC_US8:%.*]] ]
-; CHECK-NEXT:    [[INC_US9]] = add nsw i32 [[TMP9]], 1
+; CHECK-NEXT:    [[TMP7:%.*]] = phi i32 [ [[TMP6]], [[FOR_INC_LR_PH_US12]] ], [ [[INC_US9:%.*]], [[FOR_INC_US8:%.*]] ]
+; CHECK-NEXT:    [[INC_US9]] = add nsw i32 [[TMP7]], 1
 ; CHECK-NEXT:    [[EXITCOND1:%.*]] = icmp ne i32 [[INC_US9]], 1
 ; CHECK-NEXT:    br i1 [[EXITCOND1]], label [[FOR_INC_US8]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE_US13:%.*]]
 ; CHECK:       for.cond2.loopexit.us11:
 ; CHECK-NEXT:    br i1 true, label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_LCSSA_US:%.*]], label [[FOR_BODY3_US3]]
 ; CHECK:       for.inc.lr.ph.us12:
 ; CHECK-NEXT:    br label [[FOR_INC_US8]]
 ; CHECK:       for.cond8.for.cond2.loopexit_crit_edge.us13:
 ; CHECK-NEXT:    store i32 1, i32* @b, align 4
 ; CHECK-NEXT:    br label [[FOR_COND2_LOOPEXIT_US11]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa.us-lcssa.us:
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA:%.*]]
 ; CHECK:       for.body3.lr.ph.split.split:
 ; CHECK-NEXT:    br label [[FOR_BODY3:%.*]]
 ; CHECK:       for.cond8.for.cond2.loopexit_crit_edge:
 ; CHECK-NEXT:    store i32 1, i32* @b, align 4
 ; CHECK-NEXT:    br label [[FOR_COND2_LOOPEXIT:%.*]]
 ; CHECK:       for.cond2.loopexit:
 ; CHECK-NEXT:    br i1 false, label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_LCSSA:%.*]], label [[FOR_BODY3]]
 ; CHECK:       for.body3:
 ; CHECK-NEXT:    br i1 false, label [[COND_FALSE:%.*]], label [[COND_END:%.*]]
 ; CHECK:       cond.false:
 ; CHECK-NEXT:    br label [[COND_END]]
 ; CHECK:       cond.end:
-; CHECK-NEXT:    [[TMP10:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT:    [[CMP91:%.*]] = icmp slt i32 [[TMP10]], 1
+; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* @b, align 4
+; CHECK-NEXT:    [[CMP91:%.*]] = icmp slt i32 [[TMP8]], 1
 ; CHECK-NEXT:    br i1 [[CMP91]], label [[FOR_INC_LR_PH:%.*]], label [[FOR_COND2_LOOPEXIT]]
 ; CHECK:       for.inc.lr.ph:
 ; CHECK-NEXT:    br label [[FOR_INC:%.*]]
 ; CHECK:       for.inc:
-; CHECK-NEXT:    [[TMP11:%.*]] = phi i32 [ [[TMP10]], [[FOR_INC_LR_PH]] ], [ [[INC:%.*]], [[FOR_INC]] ]
-; CHECK-NEXT:    [[INC]] = add nsw i32 [[TMP11]], 1
+; CHECK-NEXT:    [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[FOR_INC_LR_PH]] ], [ [[INC:%.*]], [[FOR_INC]] ]
+; CHECK-NEXT:    [[INC]] = add nsw i32 [[TMP9]], 1
 ; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i32 [[INC]], 1
 ; CHECK-NEXT:    br i1 [[EXITCOND]], label [[FOR_INC]], label [[FOR_COND8_FOR_COND2_LOOPEXIT_CRIT_EDGE:%.*]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa.us-lcssa:
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA]]
 ; CHECK:       for.cond2.for.inc13_crit_edge.us-lcssa:
 ; CHECK-NEXT:    [[COND_LCSSA_PH:%.*]] = phi i32 [ [[INDVARS_IV]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_LCSSA]] ], [ [[INDVARS_IV]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US_LCSSA_US]] ]
 ; CHECK-NEXT:    br label [[FOR_COND2_FOR_INC13_CRIT_EDGE]]
 ; CHECK:       for.cond2.for.inc13_crit_edge:
 ; CHECK-NEXT:    [[COND_LCSSA:%.*]] = phi i32 [ [[COND_LCSSA_PH]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA]] ], [ [[COND_LCSSA_PH_US]], [[FOR_COND2_FOR_INC13_CRIT_EDGE_US_LCSSA_US]] ]
 ; CHECK-NEXT:    store i32 [[COND_LCSSA]], i32* @c, align 4
 ; CHECK-NEXT:    br label [[FOR_INC13]]
 ; CHECK:       for.inc13:
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
-; CHECK-NEXT:    [[EXITCOND4:%.*]] = icmp ne i32 [[INDVARS_IV_NEXT]], 0
-; CHECK-NEXT:    br i1 [[EXITCOND4]], label [[FOR_COND2_PREHEADER]], label [[FOR_END15:%.*]]
+; CHECK-NEXT:    [[EXITCOND2:%.*]] = icmp ne i32 [[INDVARS_IV_NEXT]], 0
+; CHECK-NEXT:    br i1 [[EXITCOND2]], label [[FOR_COND2_PREHEADER]], label [[FOR_END15:%.*]]
 ; CHECK:       for.end15:
 ; CHECK-NEXT:    ret void
 ;
 
 ; br i1 {{.*}}, label %[[for_inc13]], label %
 entry:
   %0 = load i32, i32* @a, align 4
   %tobool2 = icmp eq i32 %0, 0