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Differential D94408

[RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns
ClosedPublic

Authored by frasercrmck on Jan 11 2021, 6:17 AM.

Details

Reviewers
craig.topper
rogfer01
evandro
HsiangKai
Commits
rG7989684a2e4a: [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns
Summary

Original patch by @rogfer01.

This patch adds ISel patterns for the above operations to the
corresponding vector/vector and vector/scalar RVV instructions, as well
as extra patterns to match operand-swapped scalar/vector vfrsub and
vfrdiv.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>

Diff Detail

Event Timeline

frasercrmck created this revision.Jan 11 2021, 6:17 AM
Herald added subscribers: NickHung, luismarques, apazos and 24 others. · View Herald TranscriptJan 11 2021, 6:17 AM
frasercrmck requested review of this revision.Jan 11 2021, 6:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2021, 6:17 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B84679: Diff 315787.Jan 11 2021, 6:18 AM
craig.topper accepted this revision.Jan 11 2021, 11:27 AM

LGTM

This revision is now accepted and ready to land.Jan 11 2021, 11:27 AM
frasercrmck updated this revision to Diff 315891.Jan 11 2021, 11:47 AM

rebase on main

Harbormaster completed remote builds in B84738: Diff 315891.Jan 11 2021, 1:01 PM
Closed by commit rG7989684a2e4a: [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns (authored by frasercrmck). · Explain WhyJan 11 2021, 1:26 PM
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rG7989684a2e4a: [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
50 lines
test/
CodeGen/
RISCV/
rvv/
380 lines
380 lines
380 lines
380 lines
380 lines
380 lines
380 lines
380 lines

Diff 315923

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines foreach vti = AllIntegerVectors in {
def : VPatBinarySDNode_XI<vop, instruction_name, "VI", def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW, vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
vti.LMul, vti.RegClass, vti.RegClass, vti.LMul, vti.RegClass, vti.RegClass,
!cast<ComplexPattern>(SplatPat#_#ImmType), !cast<ComplexPattern>(SplatPat#_#ImmType),
ImmType>; ImmType>;
} }
} }
class VPatBinarySDNode_VF<SDNode vop,
string instruction_name,
ValueType result_type,
ValueType vop_type,
ValueType xop_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg RetClass,
VReg vop_reg_class,
DAGOperand xop_kind> :
Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
(vop_type (splat_vector xop_kind:$rs2)))),
(!cast<Instruction>(instruction_name#"_VF_"#vlmul.MX)
vop_reg_class:$rs1,
ToFPR32<xop_type, xop_kind, "rs2">.ret,
VLMax, sew)>;
multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
foreach vti = AllFloatVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.SEW,
vti.LMul, vti.RegClass, vti.RegClass>;
def : VPatBinarySDNode_VF<vop, instruction_name,
vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.RegClass,
vti.ScalarRegClass>;
}
}
multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in
def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)),
(fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX)
fvti.RegClass:$rs1,
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
VLMax, fvti.SEW)>;
}
multiclass VPatIntegerSetCCSDNode_VV<CondCode cc, multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
string instruction_name, string instruction_name,
bit swap = 0> { bit swap = 0> {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX); defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2), cc)), (vti.Vector vti.RegClass:$rs2), cc)),
SwapHelper<(instruction), SwapHelper<(instruction),
▲ Show 20 Lines • Show All 192 Lines • ▼ Show 20 Lines def : Pat<(mti.Mask (or VR:$rs1, (vnot VR:$rs2))),
(!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX) (!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX)
VR:$rs1, VR:$rs2, VLMax, mti.SEW)>; VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
} }
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
defm "" : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
defm "" : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">;
defm "" : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">;
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm "" : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">;
defm "" : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">;
defm "" : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">;
// 14.11. Vector Floating-Point Compare Instructions // 14.11. Vector Floating-Point Compare Instructions
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fadd <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfadd_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfadd_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfadd_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfadd_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfadd_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfadd_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfadd_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfadd_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfadd_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfadd_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfadd_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfadd_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfadd_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfadd_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfadd_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfadd_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfadd_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfadd_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfadd_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfadd_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfadd_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfadd_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fadd <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfadd_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfadd_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfadd_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfadd_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfadd_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfadd_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfadd_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfadd_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfadd_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfadd_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfadd_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfadd_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfadd_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfadd_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfadd_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfadd_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfadd_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfadd_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfadd.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfadd_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfadd_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfadd.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfadd_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfadd_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfadd_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfadd_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfadd.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfdiv_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fdiv <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfdiv_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfdiv_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfdiv_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfdiv_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfdiv_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfdiv_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfdiv_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfdiv_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfdiv_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfdiv_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfdiv_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfdiv_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfdiv_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfdiv_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfdiv_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfdiv_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfdiv_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfdiv_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfdiv_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfdiv_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfdiv_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fdiv <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfdiv_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfdiv_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfdiv_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfdiv_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfdiv_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfdiv_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfdiv_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfdiv_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfdiv_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfdiv_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfdiv_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfdiv_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfdiv_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfdiv_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfdiv_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfdiv_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfdiv_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfdiv_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfdiv.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfdiv_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfdiv_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfrdiv.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfmul_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fmul <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfmul_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfmul_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfmul_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfmul_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfmul_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfmul_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfmul_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfmul_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfmul_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfmul_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfmul_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfmul_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfmul_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfmul_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfmul_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfmul_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfmul_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfmul_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfmul_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfmul_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfmul_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfmul_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfmul_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fmul <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfmul_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfmul_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfmul_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfmul_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfmul_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfmul_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfmul_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfmul_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfmul_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfmul_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfmul_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfmul_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfmul_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfmul_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfmul_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfmul_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfmul_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfmul_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfmul.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfmul_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfmul_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfmul.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfmul_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfmul_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfmul_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfmul_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmul.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fsub <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfsub_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfsub_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfsub_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfsub_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfsub_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfsub_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfsub_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfsub_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfsub_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfsub_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfsub_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfsub_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfsub_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfsub_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfsub_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfsub_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfsub_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfsub_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfsub_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfsub_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc
}
define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc
}
define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc
}
define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc
}
define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc
}
define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc
}
define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_fv_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc
}
define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc
}
define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc
}
define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc
}
define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fsub <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc
}
define <vscale x 1 x float> @vfsub_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x float> %va, %vb
ret <vscale x 1 x float> %vc
}
define <vscale x 1 x float> @vfsub_vf_nxv1f32(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x float> %va, %splat
ret <vscale x 1 x float> %vc
}
define <vscale x 2 x float> @vfsub_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x float> %va, %vb
ret <vscale x 2 x float> %vc
}
define <vscale x 2 x float> @vfsub_vf_nxv2f32(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x float> %va, %splat
ret <vscale x 2 x float> %vc
}
define <vscale x 4 x float> @vfsub_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x float> %va, %vb
ret <vscale x 4 x float> %vc
}
define <vscale x 4 x float> @vfsub_vf_nxv4f32(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x float> %va, %splat
ret <vscale x 4 x float> %vc
}
define <vscale x 8 x float> @vfsub_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x float> %va, %vb
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfsub_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x float> %va, %splat
ret <vscale x 8 x float> %vc
}
define <vscale x 8 x float> @vfsub_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfsub_fv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x float> %splat, %va
ret <vscale x 8 x float> %vc
}
define <vscale x 16 x float> @vfsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x float> %va, %vb
ret <vscale x 16 x float> %vc
}
define <vscale x 16 x float> @vfsub_vf_nxv16f32(<vscale x 16 x float> %va, float %b) {
; CHECK-LABEL: vfsub_vf_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x float> %va, %splat
ret <vscale x 16 x float> %vc
}
define <vscale x 1 x double> @vfsub_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v17
; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x double> %va, %vb
ret <vscale x 1 x double> %vc
}
define <vscale x 1 x double> @vfsub_vf_nxv1f64(<vscale x 1 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x double> %va, %splat
ret <vscale x 1 x double> %vc
}
define <vscale x 2 x double> @vfsub_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v18
; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x double> %va, %vb
ret <vscale x 2 x double> %vc
}
define <vscale x 2 x double> @vfsub_vf_nxv2f64(<vscale x 2 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x double> %va, %splat
ret <vscale x 2 x double> %vc
}
define <vscale x 4 x double> @vfsub_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfsub.vv v16, v16, v20
; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x double> %va, %vb
ret <vscale x 4 x double> %vc
}
define <vscale x 4 x double> @vfsub_vf_nxv4f64(<vscale x 4 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x double> %va, %splat
ret <vscale x 4 x double> %vc
}
define <vscale x 8 x double> @vfsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfsub.vv v16, v16, v8
; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x double> %va, %vb
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfsub_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfsub_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vc
}
define <vscale x 8 x double> @vfsub_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: vfsub_fv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfrsub.vf v16, v16, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x double> %splat, %va
ret <vscale x 8 x double> %vc
}