[GlobalISel][TableGen] Fix seg fault for zero instruction

[ehjogab]

Summary

Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.

[ehjogab]

Bump

[bjope]

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

6

Nice that we no longer crash, but I don't know how relevant this check is. What about checking that we get the "warning: Skipped pattern: Dst pattern root isn't a known leaf" message instead?

[ehjogab]

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

6

That'd be nice, but can it be done? I'm not very familiar with FileCheck...

[ehjogab]

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

6

I missed to mention that this check at least checks that we no longer crashes, so it's not entirely useless.

[ehjogab]

Added Paul-C-Anagnostopoulos since he's now one of the TableGen code owners.

[bjope]

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

6

One solution could be to do -o /dev/null and ... 2>&1 | FileCheck %s, to simply ignore regular output, and FileCheck on both stdout and stderr (in case the warning is printed on stderr).

I'm not sure exactly how tblgen emit those warnings, which stream, or if it is conditional based on how the binary is built (e.g. using -debug in test cases usually also require that you add // REQUIRES: asserts to avoid running the test case when debug support isn't included.

But I think that simply checking for the warning would work here. FileCheck is just doing pattern matching on it's input.

[ehjogab]

Fixed testcase according to bjope's feedback

[ehjogab]

Missed a part of the CHECK

[Paul-C-Anagnostopoulos]

LGTM.

[uabelho]

I submitted this for @ehjogab

llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

+// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+// CHECK: return MatchTable
+def : Pat<(zext (i16 (trunc i32:$src))),
+          (i32 $src)>;

llvm/utils/TableGen/GlobalISelEmitter.cpp

 //===- GlobalISelEmitter.cpp - Generate an instruction selector -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   auto InsnMatcherOrError =
       createAndImportSelDAGMatcher(M, InsnMatcherTemp, Src, TempOpIdx);
   if (auto Error = InsnMatcherOrError.takeError())
     return std::move(Error);
   InstructionMatcher &InsnMatcher = InsnMatcherOrError.get();
 
   if (Dst->isLeaf()) {
     Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
-
-    const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
     if (RCDef) {
+      const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
+
       // We need to replace the def and all its uses with the specified
       // operand. However, we must also insert COPY's wherever needed.
       // For now, emit a copy and let the register allocator clean up.
       auto &DstI = Target.getInstruction(RK.getDef("COPY"));
       const auto &DstIOperand = DstI.Operands[0];
 
       OperandMatcher &OM0 = InsnMatcher.getOperand(0);
       OM0.setSymbolicName(DstIOperand.Name);