Page MenuHomePhabricator

Pierre-vh (Pierre van Houtryve)
User

Projects

User does not belong to any projects.

User Details

User Since
Dec 3 2018, 7:49 AM (93 w, 5 d)

Recent Activity

May 22 2020

Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

Rebasing the patch. (Changed code in TargetTransformInfoImpl.hpp, around line 864).

May 22 2020, 2:25 AM · Restricted Project
Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
May 22 2020, 12:01 AM · Restricted Project

May 21 2020

Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

Rebasing the patch - there's now one more call side for getCastInstrCost

May 21 2020, 2:40 AM · Restricted Project
Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 21 2020, 1:36 AM · Restricted Project
Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 21 2020, 1:03 AM · Restricted Project

May 20 2020

Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 20 2020, 12:02 PM · Restricted Project
Pierre-vh committed rG835251f7d99a: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks. (authored by Pierre-vh).
[Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 20 2020, 4:51 AM
Pierre-vh closed D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 20 2020, 4:51 AM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
  • Allow VCMPs before the VCTP
  • Add test case as requested
  • Revert the null-pointer check I added in the previous patch & refactor the condition as suggested
May 20 2020, 3:12 AM · Restricted Project

May 19 2020

Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

Re-adding the instructions in the calls to TTI::getCastInstrCost in the LoopVectorizer.

May 19 2020, 7:33 AM · Restricted Project
Pierre-vh updated the diff for D79783: [LV] Fallback strategies if tail-folding fails.
  • Addressed comments (see items marked as "done")
  • Changed "reportVectorizationFailure" calls in "prepareTailFoldingByMasking" into simple debug prints.
May 19 2020, 7:00 AM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
  • Added note explaining how instructions that write to VPR.P0 work
  • Removed the logic to check VPTs, they're acceptable whenever a VCMP is
  • Adding VPT before VCTP test case
    • It was causing a crash, which I fixed by adding a null-pointer check at line 404
  • Added new debug message at line
May 19 2020, 6:28 AM · Restricted Project
Pierre-vh updated the diff for D79783: [LV] Fallback strategies if tail-folding fails.
  • Changing implementation of the patch following discussion
  • Removed the ReportFailure argument of prepareToFoldTailByMasking. I don't think it's useful anymore, but feedback is welcome. (The only thing that annoys me is that we now print "loop not vectorized" even when we'll fallback to a scalar epilogue)
  • Added a test that makes use of the attribute that enables tail-folding
  • Simplified tests
May 19 2020, 2:08 AM · Restricted Project

May 18 2020

Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 18 2020, 1:34 AM · Restricted Project

May 15 2020

Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 15 2020, 5:13 AM · Restricted Project

May 14 2020

Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
  • Removing instruction from calls to getCastInstrCost in the LoopVectorizer.
May 14 2020, 1:01 AM · Restricted Project
Pierre-vh added a comment to D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

The general idea of passing down information about the instruction makes sense.

The one thing I would say here is that we probably shouldn't pass down the "Instruction" from the vectorizer at all: in general, the cost computation doesn't know what sort of transforms the vectorizer is going to do, so any information computed from its operands/uses will be misleading in general.

May 14 2020, 1:01 AM · Restricted Project

May 13 2020

Pierre-vh updated the diff for D79783: [LV] Fallback strategies if tail-folding fails.
May 13 2020, 7:00 AM · Restricted Project
Pierre-vh committed rG2668775f6665: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable (authored by Pierre-vh).
[LSR][ARM] Add new TTI hook to mark some LSR chains as profitable
May 13 2020, 6:27 AM
Pierre-vh closed D79418: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable.
May 13 2020, 6:27 AM · Restricted Project
Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
May 13 2020, 2:07 AM · Restricted Project
Pierre-vh updated the diff for D79163: [Target][ARM] Tune getCastInstrCost for extending masked loads and truncating masked stores.
  • Cleaning up vectorizer tests (removed all extra attributes)
  • Refactored & Improved the cast.ll test
  • Removed isLoadOrMaskedLoad, now using the CCH instead.
May 13 2020, 2:07 AM · Restricted Project

May 12 2020

Pierre-vh added inline comments to D79783: [LV] Fallback strategies if tail-folding fails.
May 12 2020, 9:39 AM · Restricted Project
Pierre-vh updated the diff for D79418: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable.
  • Simplified the vctp-chains.ll test: removed useless attributes
  • Added codegen test to test the whole pipeline (based on the vctpi32 test from vctp-chains.ll)
May 12 2020, 8:01 AM · Restricted Project
Pierre-vh added inline comments to D79418: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable.
May 12 2020, 8:01 AM · Restricted Project
Pierre-vh added reviewers for D79783: [LV] Fallback strategies if tail-folding fails: gilr, rengolin.
May 12 2020, 7:29 AM · Restricted Project
Pierre-vh created D79783: [LV] Fallback strategies if tail-folding fails.
May 12 2020, 6:57 AM · Restricted Project
Pierre-vh committed rGbf2183374a67: [Target][ARM] Replace re-uses of old VPR values with VPNOTs (authored by Pierre-vh).
[Target][ARM] Replace re-uses of old VPR values with VPNOTs
May 12 2020, 4:48 AM
Pierre-vh committed rG24bf8063d677: [Target][ARM] Replace outdated getARMVPTBlockMask function (authored by Pierre-vh).
[Target][ARM] Replace outdated getARMVPTBlockMask function
May 12 2020, 4:48 AM
Pierre-vh closed D78201: [Target][ARM] Replace outdated getARMVPTBlockMask function.
May 12 2020, 4:48 AM · Restricted Project
Pierre-vh closed D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
May 12 2020, 4:48 AM · Restricted Project

May 11 2020

Pierre-vh added inline comments to D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
May 11 2020, 6:24 AM · Restricted Project
Pierre-vh updated the diff for D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
  • Minor refactoring of the patch
  • The pass is no longer limited to VCMPs for VCCRValue, it can now use any instruction that writes to VPR (e.g. VMSR)
  • The pass no longer replaces VPNOT with copies - it just removes the VPNOT and replaces all of its uses.
  • Other minor fixes
May 11 2020, 6:24 AM · Restricted Project
Pierre-vh updated the diff for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
  • Moved CastContextHint to TargetTransformInfo
  • Moved the logic that calculates the CastContextHint from an Instruction* from getCastInstrCost (in TargetTransformInfo.cpp) to a static function in TargetTransformInfo named getCastContextHint).
  • CastContextHint is no longer an optional parameter. Callers have to choose between using a None for the context, using a custom context or calling TTI::getCastContextHint
  • Removed my change in BasicTTIImpl.h - (Should I restore it? It seemed to have no effects on tests)
May 11 2020, 3:43 AM · Restricted Project
Pierre-vh updated the diff for D79163: [Target][ARM] Tune getCastInstrCost for extending masked loads and truncating masked stores.

Updating the patch following the changes to D79162

May 11 2020, 3:43 AM · Restricted Project

May 7 2020

Pierre-vh updated the diff for D79418: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable.

Changing the implementation of the patch.

  • TTI hook renamed to isProfitableLSRChainElement
    • It now returns true for the VCTP
  • Removed FilterOutUndesirableUses
  • Now isProfitableLSRChainElement is called in LSR's isProfitableChain function. If it returns true for one of the chain's UserInst, the chain will be considered profitable and will not be optimized by LSR.
May 7 2020, 6:45 AM · Restricted Project
Pierre-vh added inline comments to D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 7 2020, 5:37 AM · Restricted Project

May 5 2020

Pierre-vh created D79418: [LSR][ARM] Add new TTI hook to mark some LSR chains as profitable.
May 5 2020, 7:30 AM · Restricted Project
Pierre-vh added a comment to D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

Yes, I originally tried an enum with one entry per "kind" of load/store, as you said. It was working fine, but I felt that it was a bit confusing, as each entry had a different meaning based on the opcode. For instance, I had the MaskedVector entry, which, for most casts, meant that the operand was a masked load, but for truncs meant that the single user of the cast is a masked store. ,What if another target needs to deal with truncs of masked loads or something like that ? They wouldn't be able to use that API, they'd have to hack it. (I don't know if this will ever come up, I'm just trying to think about all of the use cases for this enum)
With the current format of the enum, it's a clearer IMHO, there is no ambiguity, and any target can add their specific case in there and deal with it in the backend.

Of course, both versions work equally well, I'm fine with both.

I feel like a truncating load is not a very common thing. We should try and get the common case working first. Although I see your point about the other types of casts, it might be enough at the moment to only look at sext, zext and trunc. Trunc is a little different because we are looking at the operands, might not be the prettiest, but otherwise I think should be OK.

I think that we in MVE need a way to distinguish all the types of loads/stores that the vectorizer produces, even if the context instruction is incorrect and cannot be trusted. But it may be better not to think of this from an individual backend perspective exactly. We are trying to pass the information that the midend knows through to the costmodel. In that way it makes sense to me to add a parameter that has vales {None, Normal, Masked, Interleaved and Gather}, maybe reversed too as the vectorizer can produce it. Get them to be passed through to the correct places, or calculated from the context if nothing else is known. That sounds like it should be able to be done cleanly and simply enough.

I believe that extending load and truncating stores are at least the most common ones we need to worry about, (if not the only one's). Can give that a go, see how it looks?

May 5 2020, 6:25 AM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.

Change IsAcceptableVPT and adding GetReachingDefs

May 5 2020, 4:16 AM · Restricted Project
Pierre-vh abandoned D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated.

Closing this for now as we plan to fix this in LSR instead.

May 5 2020, 3:44 AM · Restricted Project
Pierre-vh committed rGd5eb7ffa3372: [Target][ARM] Fold or(A, B) more aggressively for I1 vectors (authored by Pierre-vh).
[Target][ARM] Fold or(A, B) more aggressively for I1 vectors
May 5 2020, 2:07 AM
Pierre-vh committed rGffdda495f79a: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops (authored by Pierre-vh).
[Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops
May 5 2020, 2:07 AM
Pierre-vh closed D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.
May 5 2020, 2:07 AM · Restricted Project
Pierre-vh closed D77712: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops.
May 5 2020, 2:07 AM · Restricted Project
Pierre-vh updated the diff for D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.
May 5 2020, 1:34 AM · Restricted Project

May 4 2020

Pierre-vh updated the diff for D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.
  • Refactorings (see comments marked "done")
  • Fold even when only one side is free to invert. This brings back the mve-pred-or changes.
May 4 2020, 6:22 AM · Restricted Project
Pierre-vh added inline comments to D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 4 2020, 3:42 AM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 4 2020, 2:37 AM · Restricted Project
Pierre-vh added inline comments to D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
May 4 2020, 2:05 AM · Restricted Project
Pierre-vh updated the diff for D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.
  • Moved the (not(vcmp)) -> !vcmp fold to PerformXORCombine
May 4 2020, 1:33 AM · Restricted Project

May 1 2020

Pierre-vh added a comment to D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.

Sorry, I forgot about this. Thanks for that example, I now see how the VCTP can be Else predicated, but I obviously don't quite understand how VPT predication works! The code below is what is generated from the example and now I don't understand why the VSTR is Else predicated. Is it because it needs the same inverted predicate as the VCTP, coming from the VCMP, as well as being ANDed with the VCTP? My intuition wanted it to be Then predicated after the VCTP has already done an inversion.

vctp.32 r1
vpst
vldrwt.u32      q1, [r0]
vptee.s32       ge, q1, r2
vcmpt.s32       le, q1, r3
vctpe.32        r1
vstrwe.32       q0, [r0], #16
subs    r1, #4
le      lr, .LBB0_1
May 1 2020, 3:52 AM · Restricted Project
Pierre-vh added inline comments to D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated.
May 1 2020, 12:57 AM · Restricted Project
Pierre-vh added inline comments to D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated.
May 1 2020, 12:05 AM · Restricted Project

Apr 30 2020

Pierre-vh added a comment to D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

We (ARM/MVE) need to do the same thing for the cost of gather and interleaved loads. Whether the sext/zext is free there is equally variable. The way that I would have imagined this is a enum that can be one of the types of loads that the vectorizer produces (Normal, Masked, Interleave, Gather, Expanded?). There probably needs to be an option for None or Unknown too. I understand that you tried this before but ran into trouble? Can you speak to what kinds of problems you ran into doing things that way?

Apr 30 2020, 11:51 PM · Restricted Project
Pierre-vh updated the summary of D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
Apr 30 2020, 6:46 AM · Restricted Project
Pierre-vh added a comment to D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

What do you mean by "doing it at a higher level"?

I mean that trying to attach extra bits of information to individual instruction costs hooks doesn't scale. Also, if we want to add in-depth information, such as the legalization object, then we'd probably have to create a whole new API for the vectorizer to use too. Instead, we could enable TTI to calculate the cost of the loop, not just each instruction. This would give us the freedom to evaluate all the memory operations, evaluating their extends/truncs together, and enable us to make a good decision.

Apr 30 2020, 6:12 AM · Restricted Project
Pierre-vh added a comment to D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.

This feels like a hack to me too, I think we need to move away from passing snippets of information to the instruction cost hooks. There are many other places in the vectorizer where instruction costs are calculated too. What information do we have at this point and what do we need to know? I like the sound of TTI taking something like the LoopVectorizationLegality object, but doing it at a higher level than on a per-instruction basis, allowing TTI to look at the loop.

Apr 30 2020, 4:31 AM · Restricted Project
Pierre-vh updated the summary of D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
Apr 30 2020, 3:37 AM · Restricted Project
Pierre-vh added reviewers for D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost: samparker, dmgreen, SjoerdMeijer.
Apr 30 2020, 3:01 AM · Restricted Project
Pierre-vh created D79163: [Target][ARM] Tune getCastInstrCost for extending masked loads and truncating masked stores.
Apr 30 2020, 3:01 AM · Restricted Project
Pierre-vh created D79162: [Analysis] TTI: Add CastContextHint for getCastInstrCost.
Apr 30 2020, 2:44 AM · Restricted Project

Apr 29 2020

Pierre-vh added inline comments to D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated.
Apr 29 2020, 4:47 AM · Restricted Project

Apr 28 2020

Pierre-vh created D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated.
Apr 28 2020, 4:47 AM · Restricted Project

Apr 27 2020

Pierre-vh updated the diff for D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.

Updated the patch: now the transformation only happens if one of the operands is a condition that can be immediately inverted.
It isn't as good as the other version (in terms of improvements) but it's safer (there is less risk of generating terrible code in some situations)

Apr 27 2020, 2:38 AM · Restricted Project

Apr 20 2020

Pierre-vh updated the diff for D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors.

I reworked the implementation of the patch, it should be cleaner now.

Apr 20 2020, 11:57 PM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.

Updated the patch following review.

Apr 20 2020, 3:11 AM · Restricted Project
Pierre-vh added inline comments to D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
Apr 20 2020, 3:11 AM · Restricted Project

Apr 17 2020

Pierre-vh updated the diff for D78201: [Target][ARM] Replace outdated getARMVPTBlockMask function.
  • recomputeVPTBlockMask now takes a reference instead of 2 iterators
  • Fixed assertion in recomputeVPTBlockMask
Apr 17 2020, 5:54 AM · Restricted Project
Pierre-vh updated the diff for D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
  • Added support for optimising multiple VPT blocks in the same Basic Block, and added a test to show it
  • Now VCCRValue is only set for VCMPs. (It doesn't really make a difference, but makes it clear that only VCMPs are supported by this optimisation)
Apr 17 2020, 4:50 AM · Restricted Project

Apr 16 2020

Pierre-vh added inline comments to D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
Apr 16 2020, 7:16 AM · Restricted Project
Pierre-vh updated the diff for D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
  • removing a one-line-change that didn't belong to this patch (a TTI change)
Apr 16 2020, 12:47 AM · Restricted Project

Apr 15 2020

Pierre-vh created D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks.
Apr 15 2020, 7:05 AM · Restricted Project
Pierre-vh updated the summary of D78201: [Target][ARM] Replace outdated getARMVPTBlockMask function.
Apr 15 2020, 6:32 AM · Restricted Project
Pierre-vh created D78201: [Target][ARM] Replace outdated getARMVPTBlockMask function.
Apr 15 2020, 6:32 AM · Restricted Project

Apr 14 2020

Pierre-vh committed rG13eb89013938: [Target][ARM] Fix VPT Block Pass miscompilation (authored by Pierre-vh).
[Target][ARM] Fix VPT Block Pass miscompilation
Apr 14 2020, 7:29 AM
Pierre-vh committed rG456302435625: [Target][ARM] Adding MVE VPT Optimisation Pass (authored by Pierre-vh).
[Target][ARM] Adding MVE VPT Optimisation Pass
Apr 14 2020, 7:29 AM
Pierre-vh closed D77798: [Target][ARM] Fix VPT Block Pass miscompilation.
Apr 14 2020, 7:29 AM · Restricted Project
Pierre-vh closed D76709: [Target][ARM] Adding MVE VPT Optimisation Pass.
Apr 14 2020, 7:28 AM · Restricted Project
Pierre-vh updated the diff for D77712: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops.
  • Adding if (Subtarget->hasMVEIntegerOps()) before setTargetDAGCombine(ISD::VSELECT)
Apr 14 2020, 4:13 AM · Restricted Project
Pierre-vh updated the diff for D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
  • Rebasing the patch because I inserted D77798 between this and D76709
    • D77798 also added a new test in mve-pred-not and this pass improves it as well.
Apr 14 2020, 4:13 AM · Restricted Project
Pierre-vh updated the diff for D77798: [Target][ARM] Fix VPT Block Pass miscompilation.
  • Rebasing the patch, so I can commit it earlier (I'll commit it with the VPT Optimisations pass which has already been approved)
  • Adding another test + restoring the old test (which produces a weird result, but it's fixed by the child revision)
Apr 14 2020, 3:41 AM · Restricted Project
Pierre-vh abandoned D75343: [RFC][debuginfo-tests][dexter] Add a test generation tool.

Closing for now as I'm working on other things, I'll reopen when/if I can come back to this.

Apr 14 2020, 1:33 AM · Restricted Project, debug-info

Apr 9 2020

Pierre-vh created D77798: [Target][ARM] Fix VPT Block Pass miscompilation.
Apr 9 2020, 7:01 AM · Restricted Project

Apr 8 2020

Pierre-vh updated the diff for D77712: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops.
  • Removed useless comment.
  • Now calls setTargetDAGCombine(ISD::VSELECT) everytime, but the PerformVSELECTCombine function will return early if MVE Integer Ops are not enabled.
Apr 8 2020, 11:57 PM · Restricted Project
Pierre-vh created D77712: [Target][ARM] Add PerformVSELECTCombine for MVE Integer Ops.
Apr 8 2020, 12:29 AM · Restricted Project

Apr 7 2020

Pierre-vh abandoned D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

Hello again,

Apr 7 2020, 7:34 AM · Restricted Project
Pierre-vh added a comment to D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

I had to revert this change because it seemed to have caused multiple buildbot failures:

This seems to repro locally when running check-llvm. llc hangs in an infinite loop for e.g. llvm/test/CodeGen/X86/avx512-vec-cmp.ll

Apr 7 2020, 4:17 AM · Restricted Project
Pierre-vh committed rG4fc59a468ff4: Revert "[CodeGen][SelectionDAG] Flip Booleans More Often" (authored by Pierre-vh).
Revert "[CodeGen][SelectionDAG] Flip Booleans More Often"
Apr 7 2020, 1:36 AM
Pierre-vh added a reverting change for rG23342bdcc888: [CodeGen][SelectionDAG] Flip Booleans More Often: rG4fc59a468ff4: Revert "[CodeGen][SelectionDAG] Flip Booleans More Often".
Apr 7 2020, 1:36 AM
Pierre-vh reopened D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

I had to revert this change because it seemed to have caused multiple buildbot failures:

Apr 7 2020, 1:35 AM · Restricted Project
Pierre-vh committed rG23342bdcc888: [CodeGen][SelectionDAG] Flip Booleans More Often (authored by Pierre-vh).
[CodeGen][SelectionDAG] Flip Booleans More Often
Apr 7 2020, 12:30 AM
Pierre-vh closed D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.
Apr 7 2020, 12:30 AM · Restricted Project
Pierre-vh added a comment to D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

LGTM.

Not sure if you have commit access. If you want me to commit this for you, please let me know how to credit you in the "Author" line of the git commit (name and email).

Apr 7 2020, 12:30 AM · Restricted Project

Apr 6 2020

Pierre-vh updated the diff for D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.
  • Moved the Const->getAPIntValue().sextOrTrunc(VT.getScalarSizeInBits()) expression out of the switch, storing it in ConstValue
  • Changed the ZeroOrOneBooleanContent case to use ConstValue as well
Apr 6 2020, 4:17 AM · Restricted Project

Apr 3 2020

Pierre-vh updated the diff for D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

Here is the change using VT.getScalarSizeInBits().

Apr 3 2020, 1:34 AM · Restricted Project
Pierre-vh updated the diff for D76709: [Target][ARM] Adding MVE VPT Optimisation Pass.

PrevVCMPResultKiller is now correctly reset back to nullptr, but I didn't add a test for it as it was not useful (there was nothing to test).
It's pretty much an NFC, the behaviour is the exact same as before, but it's indeed more correct to reset it once a VCMP has been replaced by a VPNOT.

Apr 3 2020, 1:02 AM · Restricted Project
Pierre-vh added inline comments to D76709: [Target][ARM] Adding MVE VPT Optimisation Pass.
Apr 3 2020, 12:30 AM · Restricted Project

Apr 2 2020

Pierre-vh added a comment to D77201: [CodeGen][SelectionDAG] Flip Booleans More Often.

That's the right idea. getNumValues() seems wrong, though.

Apr 2 2020, 8:06 AM · Restricted Project
Pierre-vh updated the diff for D76847: [Target][ARM] Replace re-uses of old VPR values with VPNOTs.
  • Fixed bugs related to isKill flags in multiple places. I now correctly change the isKill flags when needed, and I added tests for that.
  • Rebased the patch - Added the mve-vpt-blocks.ll test.
Apr 2 2020, 8:06 AM · Restricted Project