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Differential D86787

GlobalISel: Implement computeNumSignBits for G_SEXTLOAD/G_ZEXTLOAD
ClosedPublic

Authored by arsenm on Aug 28 2020, 8:08 AM.

Details

Reviewers
paquette
aemerson
aditya_nandakumar
dsanders
volkan

Diff Detail

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
18 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
71 lines

Diff 288612

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Show First 20 Lines • Show All 532 Lines • ▼ Show 20 Linesunsigned GISelKnownBits::computeNumSignBits(Register R,
} }
case TargetOpcode::G_SEXT_INREG: { case TargetOpcode::G_SEXT_INREG: {
// Max of the input and what this extends. // Max of the input and what this extends.
Register Src = MI.getOperand(1).getReg(); Register Src = MI.getOperand(1).getReg();
unsigned SrcBits = MI.getOperand(2).getImm(); unsigned SrcBits = MI.getOperand(2).getImm();
unsigned InRegBits = TyBits - SrcBits + 1; unsigned InRegBits = TyBits - SrcBits + 1;
return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1), InRegBits); return std::max(computeNumSignBits(Src, DemandedElts, Depth + 1), InRegBits);
} }
case TargetOpcode::G_SEXTLOAD: {
// FIXME: We need an in-memory type representation.
if (DstTy.isVector())
return 1;
// e.g. i16->i32 = '17' bits known.
const MachineMemOperand *MMO = *MI.memoperands_begin();
return TyBits - MMO->getSizeInBits() + 1;
}
case TargetOpcode::G_ZEXTLOAD: {
// FIXME: We need an in-memory type representation.
if (DstTy.isVector())
return 1;
// e.g. i16->i32 = '16' bits known.
const MachineMemOperand *MMO = *MI.memoperands_begin();
return TyBits - MMO->getSizeInBits();
}
case TargetOpcode::G_TRUNC: { case TargetOpcode::G_TRUNC: {
Register Src = MI.getOperand(1).getReg(); Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src); LLT SrcTy = MRI.getType(Src);
// Check if the sign bits of source go down as far as the truncated value. // Check if the sign bits of source go down as far as the truncated value.
unsigned DstTyBits = DstTy.getScalarSizeInBits(); unsigned DstTyBits = DstTy.getScalarSizeInBits();
unsigned NumSrcBits = SrcTy.getScalarSizeInBits(); unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1); unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);
▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir

Show All 26 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_8_sextload_from_1 ; GCN-LABEL: name: sext_inreg_s32_8_sextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1) ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8 ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1) %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 8 %2:_(s32) = G_SEXT_INREG %1, 8
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: sext_inreg_s32_9_sextload_from_1 name: sext_inreg_s32_9_sextload_from_1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_9_sextload_from_1 ; GCN-LABEL: name: sext_inreg_s32_9_sextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1) ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9 ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1) %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 9 %2:_(s32) = G_SEXT_INREG %1, 9
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
Show All 23 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s8 ; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s8
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1) ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8 ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1) %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
%3:_(s32) = G_SEXT_INREG %2, 8 %3:_(s32) = G_SEXT_INREG %2, 8
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: sext_inreg_s32_8_sext_from_s9 name: sext_inreg_s32_8_sext_from_s9
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s9 ; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s9
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1 ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1) ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9 ; GCN: $vgpr0 = COPY [[SEXTLOAD]](s32)
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1) %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT %1 %2:_(s32) = G_SEXT %1
%3:_(s32) = G_SEXT_INREG %2, 9 %3:_(s32) = G_SEXT_INREG %2, 9
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines bb.0:
; GCN: $vgpr0_vgpr1 = COPY [[SEXT]](<2 x s32>) ; GCN: $vgpr0_vgpr1 = COPY [[SEXT]](<2 x s32>)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1) %1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1)
%2:_(<2 x s32>) = G_SEXT %1 %2:_(<2 x s32>) = G_SEXT %1
%3:_(<2 x s32>) = G_SEXT_INREG %2, 9 %3:_(<2 x s32>) = G_SEXT_INREG %2, 9
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
---
name: sext_inreg_s32_7_zextload_from_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_7_zextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 7
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 7
$vgpr0 = COPY %2
...
---
name: sext_inreg_s32_8_zextload_from_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_8_zextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ZEXTLOAD]], 8
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 8
$vgpr0 = COPY %2
...
---
name: sext_inreg_s32_9_zextload_from_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN-LABEL: name: sext_inreg_s32_9_zextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 9
$vgpr0 = COPY %2
...